Semiconductor device defect monitoring using a plurality of temperature sensing devices in an adjacent semiconductor device

Patent metadata

Field	Value
Publication number	US-9170296-B2
Application number	US-201313960029-A
Country	US
Kind code	B2
Filing date	Aug 6, 2013
Priority date	Aug 6, 2013
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed.

First claim

What is claimed is:

1. An arrangement of semiconductor devices to monitor semiconductor defects comprising:
a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device;
a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and
the plurality of temperature sensing devices in the second semiconductor device being operable to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device from a first time T 0 to a second time T 1 is indicative of a defect in the corresponding location in the first semiconductor device.

2. The arrangement of claim 1 wherein the first semiconductor device has a plurality of dynamic random access memory (DRAM) chips with each DRAM chip comprising a plurality of DRAM cells and the second semiconductor device has a plurality of DRAM chips and wherein the temperature sensing devices are the plurality of DRAM cells in the second semiconductor device.

3. The arrangement of claim 2 wherein the plurality of DRAM cells in each of the plurality of DRAM chips in the second semiconductor device are set to the “1” state at time T 0 , indicating the presence of charge stored in the DRAM cells at time T 0 , and the number of DRAM cells in the second semiconductor device switched to the “0” state are recorded at time T 1 , indicating the absence of charge in the number of DRAM cells at time T 1 .

4. The arrangement of claim 1 wherein the plurality of temperature sensing devices are digital temperature sensors.

5. The arrangement of claim 1 wherein the plurality of sensing devices are in a logic area of the second semiconductor device and the plurality of temperature sensing devices are ring oscillators.

6. The arrangement of claim 1 wherein the first semiconductor device and the second semiconductor device are identical semiconductor devices.

7. The arrangement of claim 1 wherein each of the first and second semiconductor devices has a logic area and a memory area and wherein the first semiconductor device and the second semiconductor device are identical semiconductor devices.

8. A method of monitoring defects in a semiconductor device comprising:
arranging a first semiconductor device in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device, a plurality of through silicon vias extending between the first and second semiconductor devices to electrically connect the first and second semiconductor devices; and
sensing the temperature by the temperature sensing devices of the second semiconductor device at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device.

9. The method of claim 8 wherein the second semiconductor device has a memory area and the temperature sensing devices are digital temperature sensors in the memory area.

10. The method of claim 8 wherein the temperature sensing devices are ring oscillators.

11. The method of claim 8 wherein the second semiconductor device has a memory area and the temperature sensing devices are dynamic random access memory cells in the memory area.

12. A method of monitoring defects in a semiconductor device comprising:
arranging a first semiconductor device having a plurality of dynamic random access memory (DRAM) chips with each DRAM chip comprising a plurality of DRAM cells in proximity to a second semiconductor device having a plurality of DRAM chips, the DRAM chips in the first semiconductor device being opposed to the DRAM chips in the second semiconductor device, a plurality of through silicon vias extending between the first and second semiconductor devices to electrically connect the first and second semiconductor devices;
determining a baseline number at T 0 before use of the first and second semiconductor devices in a product comprising:
setting the DRAM cells in the second semiconductor device to the charge stored state (nominally denoted as the “1” state); and
running a test of the first semiconductor device and determining a first number of DRAM cells in the second semiconductor device which switch state to the absence of charge state (nominally denoted as the “0” state), the first number being the baseline number at T 0 ;

placing the first and second semiconductor devices in a product;
processing data by the first and second semiconductor devices; and
periodically stopping processing data and testing the first semiconductor device comprising:
setting the DRAM cells in the second semiconductor device to the charge stored state;
running a test of the first semiconductor device and determining a second number of DRAM cells in the second semiconductor device which switch state to the absence of charge state; and
comparing the second number to the baseline number at T 0 and when the second number exceeds a predetermined amount, taking corrective action and when the second number is less than a predetermined amount, returning to processing data.

Assignees

• IBM
• Globalfoundries Us 2 Llc

Inventors

• Malone Kelly
• Walsh Brian L

Classifications

• G01R31/2875 Primary

  related to heating · CPC title

• G01R31/303

  of integrated circuits (G01R31/305 - G01R31/315 take precedence) · CPC title