D-type flip-flop and clock generating circuit
US-2015358004-A1 · Dec 10, 2015 · US
US9166604B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9166604-B2 |
| Application number | US-201213455572-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 25, 2012 |
| Priority date | Apr 25, 2012 |
| Publication date | Oct 20, 2015 |
| Grant date | Oct 20, 2015 |
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Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.
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What is claimed is: 1. An apparatus, comprising: an identification block arranged to receive at least two signals from a phase detector of a phase-locked loop (PLL) device and to output an identity signal indicating that one of the at least two signals is logically true and another of the at least two signals is logically false, and outputting the identity signal when one of the at least two signals temporally leads the other of the at least two signals; a counter block arranged…
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