Timing monitor for PLL

US9166604B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9166604-B2
Application numberUS-201213455572-A
CountryUS
Kind codeB2
Filing dateApr 25, 2012
Priority dateApr 25, 2012
Publication dateOct 20, 2015
Grant dateOct 20, 2015

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Abstract

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Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.

First claim

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What is claimed is: 1. An apparatus, comprising: an identification block arranged to receive at least two signals from a phase detector of a phase-locked loop (PLL) device and to output an identity signal indicating that one of the at least two signals is logically true and another of the at least two signals is logically false, and outputting the identity signal when one of the at least two signals temporally leads the other of the at least two signals; a counter block arranged…

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What does patent US9166604B2 cover?
Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.
Who is the assignee on this patent?
Koerner Heiko, Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H03K21/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).