Methods of passivating surfaces of wide bandgap semiconductor devices

Patent metadata

Field	Value
Publication number	US-9166033-B2
Application number	US-25338708-A
Country	US
Kind code	B2
Filing date	Oct 17, 2008
Priority date	Nov 23, 2004
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

First claim

That which is claimed is:

1. A method of passivating a surface of a wide bandgap semiconductor device, comprising forming a graphitic and/or amorphous BN layer on a least a portion of a surface of a region of wide bandgap semiconductor material of the wide-bandgap semiconductor device.

2. The method of claim 1 , wherein the wide bandgap semiconductor device comprises a Group III-nitride semiconductor device.

3. The method of claim 1 , wherein the wide bandgap semiconductor device comprises a GaN based semiconductor device.

4. The method of claim 1 , wherein the wide bandgap semiconductor device comprises a Group III-nitride high electron mobility transistor.

5. The method of claim 1 , wherein forming a graphitic and/or amorphous BN layer is carried out at a temperature less than a decomposition temperature of wide bandgap semiconductor materials in the wide bandgap semiconductor device.

6. The method of claim 1 , wherein forming a graphitic and/or amorphous BN layer is carried out at a temperature less than about 1100° C.

7. The method of claim 1 , wherein forming a graphitic and/or amorphous BN layer is carried out at a temperature less than about 1000° C.

8. The method of claim 1 , wherein forming a graphitic and/or amorphous BN layer is carried out at a temperature less than about 900° C.

9. The method of claim 1 , wherein the BN layer is formed to be non-single crystal.

10. The method of claim 1 , wherein the graphitic and/or amorphous BN layer is formed to a thickness of from about 3 Å to about 1 μm.

11. The method of claim 1 , wherein forming a graphitic and/or amorphous BN layer comprises flowing TEB and NH 3 with a carrier gas.

12. A method of passivating a surface of a Group III-nitride semiconductor device, comprising forming a SiC layer on a least a portion of a surface of a region of Group III-nitride semiconductor material of the Group III-nitride semiconductor device.

13. The method of claim 12 , wherein the Group III-nitride semiconductor device comprises a GaN based semiconductor device.

14. The method of claim 12 , wherein the Group III-nitride semiconductor device comprises a Group III-nitride high electron mobility transistor.

15. The method of claim 12 , wherein forming a SiC layer is carried out at a temperature less than a decomposition temperature of Group III-nitride semiconductor materials in the Group III-nitride semiconductor device.

16. The method of claim 12 , wherein forming a SiC layer is carried out at a temperature less than about 1100° C.

17. The method of claim 12 , wherein forming a SiC layer is carried out at a temperature less than about 1000° C.

18. The method of claim 12 , wherein forming a SiC layer is carried out at a temperature less than about 900° C.

19. The method of claim 12 , wherein the SiC layer is formed to be non-single crystal.

20. The method of claim 12 , wherein forming a SiC layer comprises forming a 3C SiC layer.

21. The method of claim 12 , wherein the SiC layer is formed to a thickness of from about 3 Å to about 1 μm.

22. The method of claim 12 , wherein the SiC layer is p-type SiC.

23. The method of claim 12 , wherein the SiC layer is insulating SiC.

24. A method of fabricating a passivation structure for a Group III-nitride semiconductor device comprising:
forming a passivation layer directly an a least a portion of a surface of a region of Group III-nitride semiconductor material of the Group III-nitride semiconductor device; and
annealing the passivation layer in an oxygen containing environment.

25. The method of claim 24 , wherein the passivation layer comprises SiN and/or MgN.

26. The method of claim 24 , wherein the passivation layer comprises BN and/or SiC.

27. The method of claim 24 , wherein the passivation layer comprises SiO 2 , MgO, Al 2 O 3 , Sc 2 O 3 and/or AlN.

28. The method of claim 24 , wherein the annealing is carried out at a temperature of from about 100° C. to about 1100° C. and for a time of from about ten seconds to about one hour.

29. The method of claim 24 , wherein the oxygen containing environment comprises O 2 , O 3 , CO 2 , CO, N 2 O, D 2 O and/or NO.

30. The method of claim 24 , wherein the annealing is performed at a temperature and for a time insufficient to oxidize a structure underlying the passivation layer but sufficient to remove at least some hydrogen from the passivation layer.

31. The method of claim 24 , wherein the Group III-nitride semiconductor material comprises a GaN based material.

32. A method of fabricating a passivation structure for a Group III-nitride semiconductor device comprising:
forming a passivation layer directly on a least a portion of a surface of a region of Group III-nitride semiconductor material of the Group III-nitride semiconductor device; and
annealing the passivation layer in D 2 and/or D 2 O.

33. The method of claim 32 , wherein the passivation layer comprises SiN and/or MgN.

34. The method of claim 32 , wherein the passivation layer comprises BN and/or SiC.

35. The method of claim 32 , wherein the passivation layer comprises SiO 2 , MgO, Al 2 O 3 , Sc 2 O 3 and/or AlN.

36. The method of claim 32 , wherein the annealing is performed at a temperature and for a time insufficient to oxidize a structure underlying the passivation layer but sufficient to remove at least some hydrogen from the passivation layer or replace at least some hydrogen in the passivation layer with deuterium.

37. The method of claim 32 , wherein the Group III-nitride semiconductor material comprises a GaN based material.

Assignees

• Saxler Adam William
• Sheppard Scott
• Smith Richard Peter
• Cree Inc

Inventors

• Saxler Adam William
• Sheppard Scott
• Smith Richard Peter

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10P14/3448

  Delta-doping · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/2904

  Silicon carbide · CPC title

• H10P14/2901

  Materials · CPC title