Microelectronic package with stacked microelectronic units and method for manufacture thereof

Patent metadata

Field	Value
Publication number	US-9165911-B2
Application number	US-201414243994-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Oct 20, 2011
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts.

First claim

The invention claimed is:

1. A method of fabricating a microelectronic package comprising:
stacking a first microelectronic unit onto a second microelectronic unit,
the first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts,
the second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, an encapsulant contacting an edge of the semiconductor chip of the second microelectronic unit and having a surface extending away from such edge, the surfaces of the semiconductor chip and the encapsulant of the second microelectronic unit defining a face of the second microelectronic unit; and
then forming bond wires electrically connecting the first unit contacts with package terminals at the face of the second microelectronic unit, the package terminals being electrically connected with the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

2. The method as claimed in claim 1 , wherein the vias and the traces are deposited.

3. The method as claimed in claim 1 , wherein the first microelectronic unit is configured to predominantly provide memory storage array function.

4. The method as claimed in claim 1 , wherein the second microelectronic unit is configured to predominantly provide logic function.

5. The method as claimed in claim 1 , wherein the first microelectronic unit includes a first semiconductor chip having first chip contacts exposed at a face of the first microelectronic unit, and a second semiconductor chip whose first chip contacts are connected with the first unit contacts through electrically conductive vias extending through the encapsulant of the first microelectronic unit.

6. The method as claimed in claim 5 , wherein the first and second semiconductor chips are configured to predominantly provide memory storage array function.

7. The method as claimed in claim 5 , wherein the second semiconductor chip partially overlies the first semiconductor chip such that the first chip contacts of the second semiconductor chip are disposed beyond an edge of the first semiconductor chip.

8. The method as claimed in claim 1 , wherein the step of forming bond wires forms at least some of the bond wires to extend about an edge of the second microelectronic unit.

9. The method as claimed in claim 1 , wherein the step of forming bond wires forms at least some of the bond wires extending through a through opening in the encapsulant of the second microelectronic unit.

10. The method as claimed in claim 9 , wherein the through opening in the encapsulant of the second microelectronic unit is formed during molding of the encapsulant about the semiconductor chip of the second microelectronic unit.

11. The method as claimed in claim 10 , wherein an element having a same configuration as the through opening forms the through opening during the molding.

12. The method as claimed in claim 1 , further comprising functionally testing at least one of the first or second microelectronic units prior to the step of stacking.

13. The method as claimed in claim 1 , further comprising functionally testing each of the first or second microelectronic units prior to the step of stacking.

14. The method as claimed in claim 1 , wherein at least one of the first or second microelectronic units is of a reconstituted wafer or circuit panel.

Assignees

• Invensas Corp

Inventors

• Caskey Terrence
• Mohammed Ilyas

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title