Image sensor, image-capturing apparatus, and electronic device
US-12185003-B2 · Dec 31, 2024 · US
Data processing circuit and solid-state imaging device
US9160318B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9160318-B2 |
| Application number | US-201314030225-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 18, 2013 |
| Priority date | Sep 24, 2012 |
| Publication date | Oct 13, 2015 |
| Grant date | Oct 13, 2015 |
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Abstract
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A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.
First claim
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What is claimed is: 1. A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit comp…
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Frequently asked questions
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- What does patent US9160318B2 cover?
- A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing a…
- Who is the assignee on this patent?
- Olympus Corp
- What technology area does this patent fall under?
- Primary CPC classification H04N25/78. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).