LED on silicon substrate using zinc-sulfide as buffer layer

US9159869B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9159869-B2
Application numberUS-201414158426-A
CountryUS
Kind codeB2
Filing dateJan 17, 2014
Priority dateAug 3, 2011
Publication dateOct 13, 2015
Grant dateOct 13, 2015

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Abstract

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A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices.

First claim

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What is claimed is: 1. A method of manufacturing a light emitting device, comprising: forming a zinc-sulfide (ZnS) layer directly on a silicon substrate; forming a zinc-telluride (ZnTe) layer directly on the ZnS layer; forming a template layer on the ZnTe layer; forming an epitaxial light emitting device structure on the template layer, wherein the epitaxial light emitting device structure includes an n-type semiconductor layer, a p-type semiconductor layer and an active lay…

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What does patent US9159869B2 cover?
A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer l…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10H20/01335. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).