Semiconductor device with HCI protection region

Patent metadata

Field	Value
Publication number	US-9159803-B2
Application number	US-201213590995-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Aug 21, 2012
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.

First claim

The invention claimed is:

1. A device comprising:
a semiconductor substrate;
a drift region in the semiconductor substrate and having a first conductivity type;
a gate structure supported by the semiconductor substrate and comprising sidewall spacers;
an isolation region within the drift region, laterally spaced from the gate structure, and around which charge carriers drift on a path through the drift region during operation; and
a protection region having a second conductivity type, and disposed along a surface of the semiconductor substrate at a position adjacent the isolation region and in which at least a part of the protection region is both disposed along a channel-side sidewall of the isolation region and not disposed under the gate structure.

2. The device of claim 1 , wherein the protection region is disposed along a transition between the drift region and an accumulation region in which the charge carriers accumulate during operation before drifting on the path through the drift region.

3. The device of claim 1 , wherein the gate structure is configured to control creation of an accumulation region along the surface of the semiconductor substrate during operation, wherein the protection region is adjacent the accumulation region.

4. The device of claim 1 , wherein the gate structure is configured to control creation of a channel region along the surface of the semiconductor substrate during operation, wherein the protection region is entirely disposed along a side of the isolation region facing the channel region.

5. The device of claim 1 , further comprising a further gate structure supported by the semiconductor substrate wherein:
the first-named gate structure is configured to control creation of a channel region along the surface of the semiconductor substrate;
the further gate structure is disposed over the isolation region; and
the protection region is disposed between the first-named and further gate structures.

6. The device of claim 1 , further comprising a further gate structure supported by the semiconductor substrate wherein:
the first-named gate structure is configured to control creation of a channel region along a surface of the semiconductor substrate;
the further gate structure is disposed over the isolation region; and
the protection region is disposed below an edge of the first-named gate structure that faces the further gate structure.

7. The device of claim 1 , further comprising source and drain regions spaced from one another in the semiconductor substrate and having the first conductivity type, wherein:
the source region comprises a contact region having a first dopant concentration level configured to support an Ohmic contact and a source/drain extension region extending laterally from the contact region toward the drain region and having a second dopant concentration level lower than the first dopant concentration level; and
the protection region is doped at a level corresponding with the second dopant concentration level.

8. The device of claim 1 , further comprising
an internal region disposed adjacent the isolation region along the surface of the semiconductor substrate and having the first conductivity type;
wherein the protection region is configured as a halo region around the internal region.

9. A device comprising:
a semiconductor substrate;
a drift region in the semiconductor substrate and having a first conductivity type;
an isolation region within the drift region and around which charge carriers drift on a path through the drift region during operation; and
a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate;
source and drain regions spaced from one another in the semiconductor substrate and having the first conductivity type, wherein the source region comprises a contact region having a first dopant concentration level configured to support an Ohmic contact and a first source/drain extension region extending laterally from the contact region toward the drain region and having a second dopant concentration level lower than the first dopant concentration level; and
a second source/drain extension region within the drift region, having the first conductivity type, and disposed along a corner of the interface between the drift region and the isolation region, wherein:
the protection region is disposed around a periphery of the second source/drain extension region; and
the second source/drain extension region is doped at a level corresponding with the second dopant concentration level.

10. An electronic apparatus comprising:
a substrate; and
a transistor disposed in the substrate, the transistor comprising:
first and second semiconductor regions having a first conductivity type and between which a voltage is applied during operation;
a third semiconductor region having a second conductivity type and within which the first semiconductor region is disposed;
a fourth semiconductor region having the first conductivity type and within which the second semiconductor region is disposed;
a gate structure supported by the substrate and comprising sidewall spacers;
an isolation region within the fourth semiconductor region, laterally spaced from the gate structure, and around which charge carriers drift on a path through the fourth semiconductor region under the applied voltage; and
a fifth semiconductor region having the second conductivity type, and disposed along a surface of the substrate at a position adjacent the isolation region and in which at least a part of the fifth semiconductor region is both disposed along a channel-side sidewall of the isolation region and not disposed under the gate structure.

11. The electronic apparatus of claim 10 , wherein the fifth semiconductor region is floating.

12. The electronic apparatus of claim 10 , further comprising a further gate structure supported by the substrate wherein:
the first-named gate structure is configured to control creation of a channel region along the surface of the substrate;
the further gate structure is disposed over the isolation region; and
the fifth semiconductor region is disposed between the first-named and further gate structures.

13. The electronic apparatus of claim 10 , further comprising a further gate structure supported by the substrate wherein:
the first-named gate structure is configured to control creation of a channel region along the surface of the substrate;
the further gate structure is disposed over the isolation region; and
the fifth semiconductor region is disposed below an edge of the first-named gate structure that faces the further gate structure.

14. An electronic apparatus comprising:
a substrate; and
a transistor disposed in the substrate, the transistor comprising:
first and second semiconductor regions having a first conductivity type and between which a voltage is applied during operation, wherein the first semiconductor region comprises a contact region having a first dopant concentration level configured to support an Ohmic contact and a first source/drain extension region extending laterally from the contact region toward the second semiconductor region and having a second dopant concentration level lower than the first dopant concentration level;
a third semiconductor region having a second conductivity type and within which the first semiconductor region is disposed;
a fourth semiconductor region having the first conductivity type and within which the second semiconductor region is disposed;
an isolation region within

Assignees

• Min Won Gi
• Yang Hongning
• Zuo Jiangkai
• Freescale Semiconductor Inc

Inventors

• Min Won Gi
• Yang Hongning
• Zuo Jiangkai

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title