Antifuse element utilizing non-planar topology

Patent metadata

Field	Value
Publication number	US-9159734-B2
Application number	US-201113976087-A
Country	US
Kind code	B2
Filing date	Oct 18, 2011
Priority date	Oct 18, 2011
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

First claim

What is claimed is:

1. A semiconductor antifuse device that can be short-circuited by applying a voltage across first and second terminals of the device, comprising:
a bulk substrate;
an insulation layer on the substrate;
a fin extending from the substrate and through the insulation layer to a top of the fin, the fin configured with a tapered portion and including a channel region, a source region, and a drain region, wherein the tapered portion includes a base region that extends from the insulation layer and continues to a thinned region at the top of the fin, the thinned region being 75% or more thinner than the base region;
a dielectric isolation layer over the channel region and on the fin including the tapered portion;
a gate material on the dielectric isolation layer and including or electrically connected with the first terminal of the device; and
source and drain contacts over the source and drain regions, respectively, the source and drain contacts including or electrically connected to the second terminal of the device.

2. The device of claim 1 wherein the tapered portion of the fin has an angular shape from the base region to the thinned region.

3. The device of claim 1 wherein the tapered portion of the fin has a curved shape from the base region to the thinned region.

4. The device of claim 1 wherein the tapered portion of the fin includes a base region and a thinned region, and the thinned region is at least 90% thinner than the base region.

5. The device of claim 1 wherein the source and drain regions comprise at least one of silicon and germanium.

6. The device of claim 1 wherein the fin is part of the bulk substrate and is silicon.

7. The device of claim 1 wherein the dielectric isolation layer comprises a high-k dielectric material, and the gate material comprises polysilicon or metal.

8. The device of claim 1 wherein the tapered portion comprises a plurality of thinned portions, each of which is 75% or more thinner than the base region.

9. The device of claim 1 wherein the tapered portion is formed by at least one of oxidation, etching, and ablation.

10. The device of claim 1 wherein the antifuse device comprises one of a frigate or double-gate FinFET topology.

11. An electronic device comprising:
a printed circuit board having one or more integrated circuits, wherein at least one of the one or more integrated circuits comprises one or more semiconductor antifuse devices as defined in claim 1 .

12. The electronic device of claim 11 wherein the one or more integrated circuits includes at least one of a communication chip and a processor, and at least one of the communication chip and processor comprises the one or more semiconductor antifuse devices.

13. The electronic device of claim 11 wherein the device is a mobile computing device.

14. A semiconductor device, comprising:
at least one antifuse element, including the device of claim 1 ; and
at least one transistor element, including an additional fin extending from the substrate and through the insulation layer to a top of the additional fin, wherein the top of the additional fin is thicker than the top of the tapered fin.

15. The device of claim 14 wherein the dielectric isolation layer is over a channel region of the additional fin and the gate material is on the dielectric isolation layer on the additional fin.

16. The device of claim 14 wherein the additional fin includes source and drain regions.

17. The device of claim 14 wherein the additional comprises silicon.

18. The device of claim 14 wherein the device comprises at least one of a plurality of the antifuse elements and a plurality of the transistor elements.

19. A computing device comprising:
a printed circuit board having at least one of a communication chip and a processor, and at least one of the communication chip and processor comprises one or more semiconductor devices as defined in claim 14 .

20. A semiconductor memory device comprising an antifuse element that can be short-circuited by applying a voltage across first and second terminals of the element, the device comprising:
a bulk substrate;
an insulation layer on the substrate;
a plurality of fins, each fin extending from the substrate and through the insulation layer to a respective fin top and including a channel region, a source region, and a drain region, at least one of the fins being configured with a tapered portion to provide the antifuse element, wherein the tapered portion includes a base region that extends from the insulation layer and continuously tapers from the base region to a thinned region at the top of the fin, the thinned region being 75% or more thinner than the base region;
a dielectric isolation layer over each of the respective channel regions and on the fins;
a gate material on the dielectric isolation layer of the tapered fin and including or electrically connected with the first terminal of the antifuse element; and
source and drain contacts for source and drain regions, respectively, of the tapered fin, the source and drain contacts electrically connected to one another via the second terminal of the antifuse element.

21. A computing device comprising the semiconductor memory device of claim 20 .

22. A semiconductor memory device comprising an antifuse element that can be short-circuited by applying a voltage across first and second terminals of the element, the device comprising:
a bulk substrate;
an insulation layer on the substrate;
a plurality of fins, each fin extending from the substrate and through the insulation layer to a respective fin top and including a channel region, a source region, and a drain region, at least one of the fins being configured with a tapered portion to provide the antifuse element, wherein the tapered portion of the fin includes a base region that extends from the insulation layer and continues tapering in an uninterrupted fashion to a thinned region at the top of the fin, and the thinned region is at least 75% thinner than the base region;
a dielectric isolation layer over each of the respective channel regions and on the fins, wherein the dielectric isolation layer comprises a high-k dielectric material;
a gate material on the dielectric isolation layer of the tapered fin, wherein the gate material comprises polysilicon or metal and includes or is otherwise coupled to the first terminal of the antifuse element; and
source and drain contacts for source and drain regions, respectively, of the tapered fin, the source and drain contacts electrically connected to or including the second terminal of the antifuse element.

23. A mobile computing device comprising the semiconductor memory device of claim 22 .

Assignees

• Hafez Walid M
• Jan Chia-Hong
• Tsai Curtis
• Park Joodong
• Yeh Jeng-Ya D
• Intel Corp

Inventors

• Hafez Walid M
• Jan Chia-Hong
• Tsai Curtis
• Park Joodong
• Yeh Jeng-Ya D

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6212

  having fin-shaped semiconductor bodies having non-rectangular cross-sections · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title