Method for producing a semiconductor module arrangement

US9159698B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9159698-B2
Application numberUS-201414161022-A
CountryUS
Kind codeB2
Filing dateJan 22, 2014
Priority dateJan 24, 2013
Publication dateOct 13, 2015
Grant dateOct 13, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount, and a plurality of electrical connections each of which has a free end. Each of the connections is routed through a different passage opening in the adjustment device. The printed circuit board is pushed onto the electrical connections by each of the free ends being inserted into a different contact opening in the printed circuit board. The adjustment device is moved to a second relative position, which is different from the first relative position, with respect to the circuit mount.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for producing a semiconductor module arrangement, the method comprising: providing a semiconductor module comprising a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount and fitted to the circuit mount, a plurality of electrical connections each having a free first end and a second end electrically conductively connected to the circuit mount, wherein each of the elec…

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What does patent US9159698B2 cover?
A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount, and a plurality of electrical connections each of which has a free end. Each of the connections is ro…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W72/073. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).