Data transmission circuit and semiconductor memory device having the same

Patent metadata

Field	Value
Publication number	US-9159399-B2
Application number	US-201213607219-A
Country	US
Kind code	B2
Filing date	Sep 7, 2012
Priority date	Dec 21, 2011
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode.

First claim

What is claimed is:

1. A data transmission circuit, comprising:
first to fourth local lines;
one or more first bit line sense amplifiers configured to correspond to the first local line and correspond to one or more first bit lines, respectively;
one or more second bit line sense amplifiers configured to correspond to the second local line and correspond to one or more second bit lines, respectively;
one or more third bit line sense amplifiers configured to correspond to the…

Assignees

• Kim Seung-Bong
• Sk Hynix Inc

Inventors

• Kim Seung-Bong

Classifications

• G11C2207/005

  Physics · mapped topic

• G11C11/4097

  Physics · mapped topic

• G11C11/4087 Primary

  Physics · mapped topic

• G11C7/10 Primary

  Physics · mapped topic

• G11C7/06

  Physics · mapped topic