2D/3D analysis for abnormal tools and stages diagnosis

Patent metadata

Field	Value
Publication number	US-9158867-B2
Application number	US-201213647643-A
Country	US
Kind code	B2
Filing date	Oct 9, 2012
Priority date	Oct 9, 2012
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

First claim

What is claimed is:

1. A method for determining abnormal equipment in a semiconductor processing system, the method comprising:
processing a plurality of wafers, wherein each of the plurality of wafers undergoes a plurality of process steps, and wherein each process step is associated with a plurality of process tools, wherein each wafer is processed by one of the plurality of tools associated with each of the plurality of process steps;
providing production history associated with each of the plurality of tools at each of the plurality of process steps for each of the plurality of processed wafers;
performing an analysis of variance on the production history;
providing a plurality of measurements associated with the plurality of wafers at each process step;
performing a regression analysis on the plurality of measurements;
identifying key measurement parameters based on the regression analysis on the plurality of measurements;
identifying key process steps based on the analysis of variance on the production history;
performing an analysis of covariance on the key measurement parameters and key process steps;
ranking the key process steps based on an f-ratio associated with the analysis of covariance on the key process steps, therein ranking an abnormality of the key process steps; and
ranking the plurality of tools associated with each of the key process steps based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

2. The method of claim 1 , wherein one of the plurality of measurements associated with the plurality of wafers comprises one or more measurements from wafer acceptance testing (WAT) of processed wafers.

3. The method of claim 1 , wherein the key measurement parameters of processed wafers comprise one or more of a quiescent supply current (IDDQ), a saturation current, and a critical dimension (CD) associated with one or more of the process steps.

4. The method of claim 1 , wherein identifying the key process steps further comprises ranking a p-value of the plurality of process steps based on the analysis of variance.

5. The method of claim 4 , wherein identifying the key process steps comprises selecting process steps having a p-value less than 0.05.

6. The method of claim 1 , wherein the statistical regression analysis comprises a stepwise regression analysis of the plurality of the plurality of measurements.

7. The method of claim 1 , wherein identifying the key process steps comprises identifying two or more process steps.

8. The method of claim 1 , wherein identifying the key measurement parameters comprises identifying two or more measurement parameters.

9. The method of claim 1 , wherein the analysis of covariance further comprises a model of the key measurement parameters and key process steps.

10. A computer program product for providing semiconductor processing control, the computer program product having a non-transitory computer-readable storage medium with a computer program embodied thereon, the computer program comprising a computer program code for:
performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers;
performing a regression analysis on a plurality of measurements associated with the plurality of wafers at each process step;
identifying key measurement parameters based on the regression analysis on the plurality of measurements;
identifying key process steps based on the analysis of variance on the production history;
performing an analysis of covariance on the key measurement parameters and key process steps;
ranking the key process steps based on an f-ratio associated with the analysis of covariance on the key process steps, therein ranking an abnormality of the key process steps; and
ranking the plurality of tools associated with each of the key process steps based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

11. The computer program product of claim 10 , wherein one of the plurality of measurements associated with the plurality of wafers comprises one or more measurements from wafer acceptance testing (WAT) of processed wafers.

12. The computer program product of claim 10 , wherein the key measurement parameters of processed wafers comprise one or more of a quiescent supply current (IDDQ), a saturation current, and a critical dimension (CD) associated with one or more of the process steps.

13. The computer program product of claim 10 , wherein identifying the key process steps further comprises ranking a p-value of the plurality of process steps based on the analysis of variance.

14. The computer program product of claim 13 , wherein identifying the key process steps comprises selecting process steps having a p-value less than 0.05.

15. The computer program product of claim 10 , wherein the statistical regression analysis comprises a stepwise regression analysis of the plurality of the plurality of measurements.

16. The computer program product of claim 10 , wherein identifying the key process steps comprises identifying two or more process steps.

17. The computer program product of claim 10 , wherein identifying the key measurement parameters comprises identifying two or more measurement parameters.

18. The computer program product of claim 10 , wherein the analysis of covariance further comprises a model of the key measurement parameters and key process steps.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chun-Hsien
• Chen Jui-Long
• Chao Hui-Yun
• Mou Jong-I
• Lin Chin-Hsiang

Classifications

• G05B23/024 Primary

  Quantitative history assessment, e.g. mathematical relationships between available data; Functions therefor; Principal component analysis [PCA]; Partial least square [PLS]; Statistical classifiers, e.g. Bayesian networks, linear regression or correlation analysis; Neural networks · CPC title

• G03F7/70616

  Monitoring the printed patterns · CPC title

• G03F7/70533 Primary

  Controlling abnormal operating mode, e.g. taking account of waiting time, decision to rework or rework flow · CPC title

• H10P74/00 Primary

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title