Pixel array substrate and display panel

Patent metadata

Field	Value
Publication number	US-9158164-B2
Application number	US-201113301783-A
Country	US
Kind code	B2
Filing date	Nov 22, 2011
Priority date	Nov 22, 2010
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

A pixel array substrate and a display panel are provided. The pixel array substrate includes a substrate, scan line groups, data lines, and pixel structures. The scan line groups are disposed on the substrate. The data lines are intersected with the scan line groups. The pixel structures are connected to the scan line groups and the data lines. Each pixel structure includes an active device group, a first pixel electrode, a second pixel electrode, and a connection electrode. The first pixel electrode is located between the second pixel electrode and the n th scan line group. The connection electrode is located at a side of the first pixel electrode adjacent to one data line. The second pixel electrode is electrically connected to the active device group through the connection electrode. The connection electrode, the first pixel electrode, and the second pixel electrode are of the same layer.

First claim

What is claimed is:

1. A pixel array substrate, comprising: a substrate; a plurality of scan line groups, disposed on the substrate, wherein each of the scan line groups comprises a first scan line and a second scan line adjacent to each other; a plurality of data lines intersecting the scan line groups; and a plurality of pixel structures, electrically connected to the scan line groups and the data lines, each of the pixel structures comprising: an active device group, wherein the active device group includes a first active device and a second active device, the first active device is electrically connected to the first scan line of an n th scan line group, and an m th data line, the second active device is electrically connected to the second scan line of the n th scan line group, wherein n and m are both positive integers; a first pixel electrode, electrically connected to the first active device of the active device group; a second pixel electrode, electrically connected to the first active device and the second active device of the active device group, the first pixel electrode being located between the second pixel electrode and the n th scan line group, and the second scan line of the n th scan line group being located between the first pixel electrode and the first scan line of the n th scan line group; and a connection electrode, located at a side of the first pixel electrode adjacent to one data line, and electrically connected the second pixel electrode and the active device group, wherein the connection electrode, the first pixel electrode, and the second pixel electrode are made of the same film.

2. The pixel array substrate as claimed in claim 1 , wherein the second scan line of the n th scan line group is electrically connected to the first scan line of the (n+i) th scan line group, and i is a positive integer.

3. The pixel array substrate as claimed in claim 1 , wherein the first active device is a dual-drain thin film transistor having two drains, the first pixel electrode is electrically connected to one drain, and the second pixel electrode is electrically connected to the other drain through the connection electrode.

4. The pixel array substrate as claimed in claim 3 , wherein the second active device is electrically connected to the second pixel electrode through the other drain of the first active device.

5. The pixel array substrate as claimed in claim 1 , further comprising an insulation layer, disposed on the substrate, covering the scan line groups, the data lines, and the active device group of each of the pixel structures.

6. The pixel array substrate as claimed in claim 5 , wherein the insulation layer has a first contact opening and a second contact opening, the first pixel electrode is electrically connected to the first active device through the first contact opening, and the connection electrode is electrically connected to the first active device and the second active device through the second contact opening.

7. The pixel array substrate as claimed in claim 6 , wherein the first contact opening and the second contact opening are located between the first scan line and the second scan line of the n th scan line group.

8. The pixel array substrate as claimed in claim 6 , wherein the first contact opening and the second contact opening are located between the first pixel electrode of one pixel structure and the second pixel electrode of a preceding pixel structure.

9. The pixel array substrate as claimed in claim 6 , wherein the first contact opening and the second contact opening are located between the first pixel electrode of one pixel structure and the second scan line of the corresponding scan line group.

10. The pixel array substrate as claimed in claim 1 , wherein each of the pixel structures further includes a coupling electrode, located on the other side of the first pixel electrode adjacent to another data line, and the coupling electrode is electrically connected to the second pixel electrode, wherein one side of the first pixel electrode is not surrounded by an electrode directly connected to the coupling electrode and the connection electrode.

11. The pixel array substrate as claimed in claim 10 , wherein the coupling electrode and the second pixel electrode are made of the same film.

12. The pixel array substrate as claimed in claim 1 , further comprising a color filter layer, disposed on the substrate.

13. The pixel array substrate as claimed in claim 1 , further comprising a black matrix layer, disposed on the substrate, and at least partially overlapping with the scan line groups and the data lines.

14. The pixel array substrate as claimed in claim 1 , wherein the second pixel electrode of the each of the pixel structures partially overlaps with at least one of the adjacent data lines.

15. The pixel array substrate as claimed in claim 14 , wherein the connection electrode partially overlaps with at least one of the adjacent data lines.

16. The pixel array substrate as claimed in claim 1 , wherein the first pixel electrode and the second pixel electrode of the each of the pixel structures respectively have a plurality of slits to define at least four alignment directions.

17. A display panel, comprising: the pixel array substrate according to claim 1 ; an opposite substrate, disposed opposite to the pixel array substrate; and a polymer stabilized alignment liquid crystal layer, disposed between the pixel array substrate and the opposite substrate.

18. The display panel as claimed in claim 17 , further comprising a patterned phase retarder, disposed on the opposite substrate, wherein the patterned phase retarder includes a plurality of phase retardation areas, and each of the phase retardation areas corresponds to one of the pixel structures.

Assignees

• Tseng Chin-An
• Ho Sheng-Ju
• Ting Tien-Lun
• Tsao Cheng-Han
• Huang Ming-Yung
• Huang Yen-Heng
• Liao Pei-Chun
• Hsu Wen-Hao
• Au Optronics Corp

Inventors

• Tseng Chin-An
• Ho Sheng-Ju
• Ting Tien-Lun
• Tsao Cheng-Han
• Huang Ming-Yung
• Huang Yen-Heng
• Liao Pei-Chun
• Hsu Wen-Hao

Classifications

• G09G2300/0443

  with several sub-pixels for the same colour in a pixel, not specifically used to display gradations (G09G3/364 takes precedence) · CPC title

• G02F1/134336 Primary

  Matrix · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title

• G02B30/25

  using polarisation techniques · CPC title

• G09G3/003

  to produce spatial visual effects · CPC title