Connector
US-9225119-B2 · Dec 29, 2015 · US
Multi-layer printed circuit board structure, connector module and memory storage device
US9155189B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9155189-B1 |
| Application number | US-201414297646-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jun 6, 2014 |
| Priority date | Apr 18, 2014 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A multi-layer printed circuit board (MLPCB) structure, suitable for being connected with a connector, wherein the connector comprises at least one connection terminal, the MLPCB structure comprising: a first layout layer, comprising: a shielding element, configured to provide a grounding voltage; and at least one pad, coupled to the at least one connection terminal; and a second layout layer, disposed corresponding to the first layout layer and compr…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H05K1/0219Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9155189B1 cover?
- A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the…
- Who is the assignee on this patent?
- Phison Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H05K1/0219. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).