Integrated circuit package including in-situ formed cavity

Patent metadata

Field	Value
Publication number	US-9153551-B2
Application number	US-201414536068-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Dec 26, 2007
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate.

First claim

What is claimed is:

1. A flip chip packaged component comprising:
a die having a first surface;
a dielectric barrier disposed on the first surface of the die, the dielectric barrier at least partially surrounding a designated location on the first surface of the die;
a plurality of bumps disposed on the first surface of the die, the plurality of bumps being located on an opposite side of the dielectric barrier from the designated location;
a substrate including a plurality of bonding pads on a second surface of the substrate, the die bonded to the substrate in a flip chip configuration, the plurality of bumps bonded to the plurality of bonding pads, the dielectric barrier contacting the substrate;
a cavity defined by the first surface of the die, the dielectric barrier, and the substrate, the cavity being proximate the designated location on the first surface of the die; and
a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die and contacting the opposite side of the dielectric barrier from the designated location, the dielectric barrier preventing the molding compound from entering the cavity.

2. The component of claim 1 wherein the plurality of bumps include a conductive material.

3. The component of claim 2 wherein the plurality of bumps include gold bumps.

4. The component of claim 3 wherein the plurality of bonding pads are gold-plated bonding pads.

5. The component of claim 2 wherein the plurality of bumps include copper pillar bumps.

6. The component of claim 1 wherein the cavity is free of the molding compound.

7. The component of claim 1 wherein the dielectric barrier includes SU8 polymer.

8. A flip chip semiconductor component package comprising:
a die having a plurality of connection bumps formed on a first surface thereof;
a substrate having a corresponding plurality of conductive bonding pads formed on a second surface thereof, the plurality of connection bumps on the first surface of the die bonded to the plurality of conductive bonding pads on the second surface of the substrate;
a dielectric barrier disposed on the first surface of the die, the dielectric barrier at least partially surrounding a designated location on the first surface of the die, the designated location being free of any of the plurality of connection bumps, the dielectric barrier bonded to the substrate with a gap-free bond;
a cavity defined by the dielectric barrier between the first surface of the die and the substrate; and
a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die, the dielectric barrier preventing the molding compound from entering the cavity.

9. The package of claim 8 wherein the plurality of conductive bonding pads are gold-plated bonding pads and the plurality of connection bumps include gold bumps.

10. The package of claim 8 wherein the die includes a MEMS device.

11. The package of claim 10 wherein the MEMS device is at least partially disposed within the designated location.

12. The package of claim 8 wherein the dielectric barrier completely surrounds the designated location.

13. The package of claim 8 wherein the dielectric barrier includes SU8 polymer.

14. A flip chip semiconductor component package comprising:
a die having a plurality of connection bumps formed on a first surface thereof;
a substrate having a corresponding plurality of conductive bonding pads formed on a second surface thereof, the plurality of connection bumps on the first surface of the die bonded to the plurality of conductive bonding pads on the second surface of the substrate;
a dielectric barrier disposed on the second surface of the substrate and bonded to the die with a gap-free bond;
a cavity defined by the dielectric barrier between the first surface of the die and the substrate; and
a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die, the dielectric barrier preventing the molding compound from entering the cavity.

15. The package of claim 14 wherein the dielectric barrier includes SU8 polymer.

16. The package of claim 14 wherein the plurality of conductive bonding pads are gold-plated bonding pads and the plurality of connection bumps include gold bumps.

17. The package of claim 14 wherein the die includes a MEMS device.

18. The package of claim 14 wherein the dielectric barrier completely surrounds the cavity.

19. The package of claim 18 wherein the cavity is free of any of the plurality of connection bumps.

20. The package of claim 14 wherein the cavity is a resonant cavity.

Assignees

• Skyworks Solutions Inc

Inventors

• Liang Steve X

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07233

  Ultrasonic bonding, e.g. thermosonic bonding · CPC title