Thermal enhanced high density flip chip package

Patent metadata

Field	Value
Publication number	US-9153530-B2
Application number	US-201113162064-A
Country	US
Kind code	B2
Filing date	Jun 16, 2011
Priority date	Jun 16, 2011
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
an IC die;
a routing layer coupled to a surface of the IC die, wherein the routing layer includes:
a plurality of metallic traces including a first metallic trace, and
a molding portion surrounding the plurality of metallic traces, wherein a thickness of the first metallic trace is substantially equal to a thickness of the molding portion, wherein a side portion of the molding portion is coupled to a side po…

Assignees

• Zhong Chonghua
• Hu Kunzhong
• Broadcom Corp

Inventors

• Zhong Chonghua
• Hu Kunzhong

Classifications

• H10W90/726

  Electricity · mapped topic

• H10W90/724

  Electricity · mapped topic

• H10W90/701

  Electricity · mapped topic

• H10W70/05

  Electricity · mapped topic

• H10W70/635 Primary

  Electricity · mapped topic