Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods

US9152595B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9152595-B2
Application numberUS-201213654653-A
CountryUS
Kind codeB2
Filing dateOct 18, 2012
Priority dateOct 18, 2012
Publication dateOct 6, 2015
Grant dateOct 6, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

First claim

Opening claim text (preview).

What is claimed is: 1. A hybrid ring bus interconnect for a processor-based system, comprising: a plurality of ring buses in a semiconductor die each of the plurality of ring buses having a bus width and configured to receive bus transaction messages from at least one requester device; and at least one inter-ring router in the semiconductor die coupled o the plurality of ring buses; the at least one inter-ring router configured to dynamically direct the bus transaction messages among the plurality of ring buses based on bandwidth performance requirements of the at least one requester device. 2. The hybrid ring bus interconnect of claim 1 , wherein the plurality of ring buses comprises a plurality of local ring buses and a plurality of global ring buses; the at least one inter-ring router configured to dynamically direct the bus transaction messages from a local ring bus among the plurality of local ring buses to a global ring bus among the plurality of global ring buses based on the bandwidth performance requirements of the at least one requester device. 3. The hybrid ring bus interconnect of claim 2 , wherein the at least one inter-ring router comprises a plurality of inter-ring routers, each of the plurality of inter-ring routers configured to dynamically direct the bus transaction messages from the local ring bus among the plurality of local ring buses to the global ring bus among the plurality of global ring buses based on the bandwidth performance requirements of the at least one requester device. 4. The hybrid ring bus interconnect of claim 1 , further comprising at least one transmit ring bus and at least one receive ring bus in the plurality of ring buses. 5. The hybrid ring bus interconnect of claim 1 , further comprising a resource manager configured to control the at least one inter-ring router to direct the bus transaction messages among the plurality of ring buses based on the bandwidth performance requirements of the at least one requester device. 6. The hybrid ring bus interconnect of claim 5 , wherein the resource manager is further configured to frequency scale each of the plurality of ring buses independently. 7. The hybrid ring bus interconnect of claim 5 , wherein the resource manager is further configured to activate and deactivate each of the plurality of ring buses independently. 8. The hybrid ring bus interconnect of claim 7 , wherein the resource manager is further configured to deactivate at least one ring bus among the plurality of ring buses in response to receiving a lower power mode update. 9. The hybrid ring bus interconnect of claim 8 , wherein the resource manager is further configured to reactivate the at least one ring bus in response to receiving a higher power mode update. 10. The hybrid ring bus interconnect of claim 5 , wherein the resource manager is further configured to change the bus width of each of the plurality of ring buses. 11. The hybrid ring bus interconnect of claim 1 , further comprising at least two different voltage rails wherein each of the plurality of ring buses is powered by one of the at least two different voltage rails. 12. The hybrid ring bus interconnect of claim 1 integrated into at least one semiconductor die. 13. The hybrid ring bus interconnect of claim 1 , further comprising a device selected from the group consisting of: a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which the hybrid ring bus interconnect is integrated. 14. The hybrid ring bus interconnect of claim 1 , wherein the at least one inter-ring router comprises a plurality of inter-ring routers each configured to dynamically direct the bus transaction messages among the plurality of ring buses based on the bandwidth performance requirements of the at least one requester device. 15. A hybrid ring bus interconnect means, comprising: a means for receiving bus transaction messages from at least one requester device and routing the bus transaction messages in a ring of a plurality of rings in a semiconductor die, each of the plurality of rings having a bus width; and a means for dynamically directing the bus transaction messages among the plurality of rings based on bandwidth performance requirements of the at least one requester device. 16. A method of directing bus transaction messages in a hybrid ring interconnect, comprising: receiving bus transaction messages from at least one requester device; directing the bus transaction messages onto a ring bus among a plurality of ring buses in a semiconductor die, each of the plurality of ring buses having a bus width and configured to receive the bus transaction messages; and dynamically directing from at least one inter-ring router in the semiconductor die coupled to the ring bus, the bus transaction messages from the ring bus to another ring bus among the plurality of ring buses based on bandwidth performance requirements of the at least one requester device. 17. The method of claim 16 , wherein the plurality of ring buses comprises a plurality of local ring buses and a plurality of global ring buses; wherein dynamically directing the bus transaction messages further comprises dynamically directing from the at least one inter-ring router, the bus transaction messages from a local ring bus among the plurality of local ring buses to a global ring bus among the plurality of global ring buses based on the bandwidth performance requirements of the at least one requester device. 18. The method of claim 17 , wherein dynamically directing the bus transaction messages comprises dynamically directing, from a plurality of inter-ring routers, the bus transactions messages from the local ring bus among the plurality of local ring buses to the global ring bus among the plurality of global ring buses based on the bandwidth performance requirements of the at least one requester device. 19. The method of claim 16 , further comprising deactivating at least one ring bus among the plurality of ring buses based on the bandwidth performance requirements. 20. The method of claim 19 , further comprising reactivating the at least one ring bus based on the bandwidth performance requirements. 21. The method of claim 16 , comprising dynamically directing, from the at least one inter-ring router in the semiconductor die coupled to the ring bus, the bus transaction messages from the ring bus to the another ring bus among the plurality of ring buses based on the bandwidth performance requirements of the at least one requester device. 22. A resource manager for controlling a hybrid ring bus interconnect, wherein the resource manager is configured to: determine whether a plurality of bus transaction requesters are active; determine bandwidth performance requirements of each active bus transaction requester; calculate a topology of the hybrid ring bus interconnect in a semiconductor die based on the bandwidth performance requirements of the active bus transaction requesters; and modify a configuration of at least one inter-ring router to dynamically route bus trans

Assignees

Inventors

Classifications

  • by switching off individual functional units in the computer system · CPC title

  • with decentralised access control · CPC title

  • using bus bridges (G06F13/4022 takes precedence) · CPC title

  • Cross-Sectional Technologies · mapped topic

  • Coupling between buses · CPC title

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What does patent US9152595B2 cover?
Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The process…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/4027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).