Memory performance when speculation control is enabled, and instruction therefor
US-2015378915-A1 · Dec 31, 2015 · US
US9152452B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9152452-B2 |
| Application number | US-201213598448-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 29, 2012 |
| Priority date | Aug 29, 2012 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and the mask size to select a first portion of the IV. The first portion of the IV and the base address value are summed to generate a memory address. The memory address is used to read a word containing multiple result values and multiple reference values from memory. A second portion of the IV is compared with each reference value using a comparator circuit. A result value associated with the matching reference value is selected using a multiplexing circuit and a select value generated by the comparator circuit. The TM sends the selected result value to the processor.
Opening claim text (preview).
What is claimed is: 1. A method comprising: (a) receiving a lookup command onto a transactional memory, wherein the transactional memory includes a lookup engine and a memory unit; (b) receiving an input value (IV); (c) selecting a first portion of the IV and a second portion of the IV; (d) reading a word out of the memory unit, wherein the word includes a plurality of result values and a plurality of reference values; (e) storing the result values, the reference values, a…
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