Method for forming separate narrow lines, method for fabricating memory structure, and product thereof

Patent metadata

Field	Value
Publication number	US-9147692-B2
Application number	US-201314143767-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 30, 2013
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.

First claim

What is claimed is:

1. A method for forming separate narrow lines, comprising:
forming a target layer over a substrate;
forming a plurality of base patterns over the target layer;
forming, as spacers on sidewalls of the base patterns, a plurality of target line patterns and a plurality of connection patterns between ends of the target line patterns;
removing the base patterns;
transferring the target line patterns and the connection patterns to the target layer to form a p…

Assignees

• Macronix Int Co Ltd

Inventors

• Yang Chin-Cheng

Classifications

• H10W20/0698

  Electricity · mapped topic

• H10D89/10 Primary

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• G11C5/063

  Physics · mapped topic

• H01L21/76895

  Electricity · mapped topic