Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Method for forming semiconductor device
US9147686B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147686-B2 |
| Application number | US-201113271874-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 12, 2011 |
| Priority date | Oct 21, 2010 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor device, the method comprising: forming a first transistor including a gate, and a first diffusion layer in a cell region of a semiconductor substrate, the first diffusion layer including a source region and a drain region; forming a second transistor including a second diffusion layer in a peripheral circuit region of the semiconductor substrate; forming a first contact layer comprising silicon, the first contact laye…
Assignees
Inventors
Classifications
- H10W20/089Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9147686B2 cover?
- A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is fo…
- Who is the assignee on this patent?
- Sako Nobuyuki, Hasunuma Eiji, Ps4 Luxco Sarl
- What technology area does this patent fall under?
- Primary CPC classification H10W20/089. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).