Memory process

Patent metadata

Field	Value
Publication number	US-9147604-B2
Application number	US-201414582899-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Aug 21, 2012
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.

First claim

What is claimed is:

1. A memory process, comprising:
providing a substrate, wherein the substrate has therein a plurality of trenches and a plurality of conductive lines buried in the trenches and has thereon an array area, and each of the conductive lines has an array portion in the array area;
defining a contact area apart from the array area on the substrate, wherein each of the conductive lines has a contact portion in the contact area;
etching the substrate between the co…

Assignees

• Nanya Technology Corp

Inventors

• Gopalan Vivek
• Kerr Robert
• Tsai Hung-Ming

Classifications

• H10W20/081

  Electricity · mapped topic

• H10W20/056 Primary

  Electricity · mapped topic

• H01L21/76802

  Electricity · mapped topic

• H01L27/108

  Electricity · mapped topic

• H01L21/76883 Primary

  Electricity · mapped topic