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Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage source
US9147498B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147498-B2 |
| Application number | US-201313862513-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 15, 2013 |
| Priority date | Apr 15, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell.
First claim
Opening claim text (preview).
What is claimed is: 1. A circuit arrangement, comprising: a memory comprising a memory cell array comprising a plurality of memory cells; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit comprising: at least one test memory cell, wherein the at least one test memory cell comprises a first test memory cell co…
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Physics · mapped topic
- G11C29/021Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9147498B2 cover?
- A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory …
- Who is the assignee on this patent?
- Bonet Zordan Leonardo Henrique, Bosio Alberto, Girard Patrick, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification G11C29/021. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).