Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US9147487B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147487-B2 |
| Application number | US-201213688623-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 29, 2012 |
| Priority date | Nov 29, 2012 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range.
Opening claim text (preview).
What is claimed is: 1. A method for programming a memory cell of a memory device, the method comprising steps of: setting up a plurality of cycle number ranges and a current program-verification cycle number; determining a specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification when the current program-verification cycle number is within the specific cycle number range; and applying a first bias volta…
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