Partial block read voltage offset
US-2024071506-A1 · Feb 29, 2024 · US
US9147486B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147486-B2 |
| Application number | US-201314018938-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 5, 2013 |
| Priority date | Sep 5, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate.
Opening claim text (preview).
What is claimed is: 1. A method for operating memory, comprising: continuously monitoring an error rate associated with sense operations performed on a group of memory cells, wherein the continuous monitoring includes: determining a current error rate associated with each of a particular number of sense operations currently performed on the memory cells of the group; and summing the current error rates; and continuously adjusting a sensing voltage used to determine a state…
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