Semiconductor memory apparatus

Patent metadata

Field	Value
Publication number	US-9147481-B2
Application number	US-201313842876-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Apr 27, 2012
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read.

First claim

What is claimed is:

1. A semiconductor memory apparatus comprising:
a memory cell array including a NAND string, the NAND string including a memory cell;
a source connected to the NAND string, a source voltage being supplied to the source;
a bit line connected to the NAND string;
a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, another end of the current path of the first transistor being conne…

Assignees

• Toshiba Kk

Inventors

• Kamata Yoshihiko

Classifications

• G11C16/26 Primary

  Physics · mapped topic

• G11C16/30

  Physics · mapped topic

• G11C16/0483

  Physics · mapped topic

• G11C16/28

  Physics · mapped topic