Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US9147449B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147449-B2 |
| Application number | US-201313861970-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2013 |
| Priority date | Feb 26, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.
Opening claim text (preview).
What is claimed is: 1. A multi-level cell (MLC) memory, comprising: a memory cell; a first reference circuit generating a first reference current, a first reference voltage and a first clamp voltage; a second reference circuit generating a second reference current, a second reference voltage and a second clamp voltage; a current supplying circuit comprising a first current source, and receiving the first clamp voltage to develop a first cell current passing through the memo…
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