Scalable serializer

Patent metadata

Field	Value
Publication number	US-9143164-B2
Application number	US-201313968200-A
Country	US
Kind code	B2
Filing date	Aug 15, 2013
Priority date	May 25, 2011
Publication date	Sep 22, 2015
Grant date	Sep 22, 2015

Abstract

According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

First claim

The invention claimed is:

1. A serializer comprising:
upper and lower shift registers configured to perform a load function wherein parallel input data is loaded from a parallel input bus and a shift function wherein said parallel input data is shifted to an output register;
said output register configured to alternately receive all of said parallel input data from said upper shift register followed by all of said parallel input data from said lower shift register over a plurality of consecutive time periods.

2. The serializer of claim 1 , wherein said upper and lower shift registers are configured to perform said shift function at a frequency of a shift clock and wherein said load function of said upper and lower shift registers is performed at a frequency of a load clock.

3. The serializer of claim 2 , wherein said parallel input bus has a number of channels, said frequency of said load clock being equal to said frequency of said shift clock divided by said number of channels.

4. The serializer of claim 1 , wherein said upper and lower shift registers are configured to perform said shift function at a frequency of a shift clock, said output register configured to alternately receive said parallel input data from said upper shift register and said parallel input data from said lower shift register at said frequency of said shift clock.

5. The serializer of claim 1 , wherein said upper and lower shift registers are configured to perform said load function and said shift function by selectively receiving a load clock and a shift clock.

6. The serializer of claim 1 , wherein said upper and lower shift registers are configured to select between performing said load function and said shift function responsive to a respective function select clock.

7. The serializer of claim 6 , wherein said respective function select clock of said upper shift register is an in inverse of said respective function select clock of said lower shift register.

8. The serializer of claim 6 , wherein said output register is configured to select between receiving said parallel input data from said upper shift register and said parallel input data from said lower shift register responsive to one of said respective function select clocks.

9. The serializer of claim 1 , wherein said upper and lower shift register comprise scan flip-flops, said scan flip-flops having first and second data inputs, said first data inputs are configured to load said parallel input data from said parallel input bus and said second data inputs are connected in cascade.

10. The serializer of claim 1 , wherein said output register is a flip-flop.

11. The serializer of claim 1 , wherein said output register is a scan flip-flop having a first data input configured to receive said parallel input data from said upper shift register and a second data input configured to receive said parallel input data from said lower shift register.

12. A serializer comprising:
upper and lower shift registers configured to perform a load function wherein parallel input data is loaded from a parallel input bus and a shift function wherein said parallel input data is shifted to an output register; and
the output register directly connected to each of the upper and lower shift registers and configured to alternately receive all of the parallel input data from the upper shift register followed by all of the parallel input data from the lower shift register over a plurality of consecutive time periods.

13. The serializer of claim 12 , wherein
the upper and lower shift registers are configured to perform the shift function at a frequency of a shift clock, and
the load function of the upper and lower shift registers is performed at a frequency of a load clock.

14. The serializer of claim 13 , wherein
the parallel input bus has a number of channels, and
the frequency of the load clock is equal to the frequency of the shift clock divided by the number of channels.

15. The serializer of claim 12 , wherein
the upper and lower shift registers are configured to perform the shift function at a frequency of a shift clock, and
the output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register at the frequency of the shift clock.

16. The serializer of claim 12 , wherein
the upper and lower shift registers are configured to perform the load function and the shift function by selectively receiving a load clock and a shift clock.

17. The serializer of claim 12 , wherein
the upper and lower shift registers are configured to select between performing the load function and the shift function responsive to a respective function select clock.

18. The serializer of claim 17 , wherein
the respective function select clock of the upper shift register is an in inverse of the respective function select clock of the lower shift register.

19. A serializer comprising:
upper and lower shift registers configured to perform a load function wherein parallel input data is loaded from a parallel input bus and a shift function wherein the parallel input data is shifted to an output register; and
the output register directly connected to each of the upper and lower shift registers and configured to receive all of the parallel input data from the upper shift register during a first predetermined period while not receiving any of the parallel input data from the lower shift register, and receive all of the parallel input data from the lower shift register during a second predetermined period, which is different from the first predetermined period, while not receiving any of the parallel input data from the upper shift register.

Assignees

• Broadcom Corp

Inventors

• Chen hua-feng
• Chandrasekharan Karthik
• Gorti Ramamurthy
• Djaja Gregory
• Smith Douglas

Classifications

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title