Semiconductor component with a semiconductor via

Patent metadata

Field	Value
Publication number	US-9142665-B2
Application number	US-96486510-A
Country	US
Kind code	B2
Filing date	Dec 10, 2010
Priority date	Dec 10, 2010
Publication date	Sep 22, 2015
Grant date	Sep 22, 2015

Abstract

A method for producing a semiconductor component includes providing a semiconductor body with a first surface and a second surface opposite the first surface, forming an insulation trench which extends into the semiconductor body from the first surface and which in a horizontal plane of the semiconductor body has a geometry such that the insulation trench defines a via region of the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, removing semiconductor material of the semiconductor body from the second surface to expose at least parts of the first insulation layer, to remove at least parts of the first insulation layer, or to leave at least partially a semiconductor layer with a thickness of less than 1 μm between the first insulation layer and the second surface, and forming first and second contact electrodes on the via region.

First claim

What is claimed is:

1. A semiconductor component, wherein the semiconductor component is implemented as an MOS transistor, the semiconductor component comprising:
a semiconductor body with a first surface and a second surface;
a first contact electrode in a region of the first surface;
a second contact electrode in a region of the second surface;
a first insulation layer defining a via region in a horizontal direction of the semiconductor body;
a monocrystalline semiconductor region arranged in the via region and extending between the first contact electrode and the second contact electrode;
a gate electrode electrically connected to the first contact electrode in the region of the first surface;
a source region arranged below the first surface;
a source electrode electrically connected to the source region, electrically insulated from the gate electrode, and arranged at least partially above the first surface; and
a drain electrode electrically insulated from the second contact electrode on the second surface,
wherein the MOS transistor comprises a gate terminal formed by the second contact electrode arranged on the second surface, wherein the gate terminal is electrically connected to a gate-electrode of the MOS transistor through the via region, and wherein the gate-electrode is formed next to the first surface and disposed outside of the via region.

2. The semiconductor component of claim 1 , wherein the first insulation layer forms a closed loop in a horizontal plane parallel to the first surface of the semiconductor body, and wherein the closed loop encloses the via region.

3. The semiconductor component of claim 2 , wherein the closed loop has a rectangular or ellipsoidal geometry in the horizontal plane.

4. The semiconductor component of claim 1 , wherein the first insulation layer together with an edge of the semiconductor body forms a closed loop in a horizontal plane of the semiconductor body parallel to the first surface, and wherein the closed loop encloses the via region.

5. The semiconductor component of claim 1 , further comprising a second insulation layer on the second surface which extends to the first insulation layer.

6. The semiconductor component of claim 5 , wherein the second insulation layer comprises at least one of an oxide layer, a nitride layer, a spin-on glass, and an imide.

7. The semiconductor component of claim 1 , wherein the first insulation layer comprises at least one of an oxide layer, a nitride layer and a low-k-dielectric.

8. The semiconductor component of claim 1 , further comprising, in a vertical cross-section substantially orthogonal to the first surface, two insulation trenches extending between the first surface and the second surface, wherein the first insulation layer is formed on adjacent sidewalls of the two insulation trenches.

9. The semiconductor component of claim 8 , wherein the two insulation trenches include an electrically conductive filling material.

10. The semiconductor component of claim 8 , wherein each of the two insulation trenches forms a closed loop in a horizontal plane parallel to the first surface of the semiconductor body, and wherein the semiconductor via region is disposed between the two insulation trenches.

11. The semiconductor component of claim 1 , further comprising at least one of a doped contact portion of the monocrystalline semiconductor region formed at the first surface, a doped contact portion of the monocrystalline semiconductor region formed at the second surface, and a doped portion of the monocrystalline semiconductor region formed at the first insulation layer.

12. The semiconductor component of claim 1 , further comprising a contact trench in the via region which is at least partially filled with an electrically conductive material extending to the second surface.

13. The semiconductor component of claim 12 , wherein a third insulation layer is formed along sidewalls of the contact trench.

14. The semiconductor component of claim 1 , wherein the first insulation layer extends between the first surface and the second surface.

15. The semiconductor component of claim 1 , wherein the gate-electrode is either arranged in a trench extending from the first surface or is arranged above the first surface.

16. A semiconductor component, wherein the semiconductor component is implemented as an MOS transistor, the semiconductor component comprising:
a semiconductor body with a first surface and a second surface;
a first contact electrode in a region of the first surface;
a second contact electrode in a region of the second surface;
a first insulation layer defining a via region in a horizontal direction of the semiconductor body;
a monocrystalline semiconductor region arranged in the via region and extending between the first contact electrode and the second contact electrode;
a gate electrode electrically connected to the first contact electrode in the region of the first surface;
a source region arranged below the first surface;
a source electrode electrically connected to the source region, electrically insulated from the gate electrode, and arranged at least partially above the first surface;
a drain electrode electrically insulated from the second contact electrode on the second surface,
wherein the first insulation layer forms a closed loop in a horizontal plane parallel to the first surface of the semiconductor body, and wherein the closed loop encloses the via region.

17. A semiconductor component, wherein the semiconductor component is implemented as an MOS transistor, the semiconductor component comprising:
a semiconductor body with a first surface and a second surface;
a first contact electrode in a region of the first surface;
a second contact electrode in a region of the second surface;
a first insulation layer defining a via region in a horizontal direction of the semiconductor body;
a monocrystalline semiconductor region arranged in the via region and extending between the first contact electrode and the second contact electrode;
a gate electrode electrically connected to the first contact electrode in the region of the first surface;
a source region arranged below the first surface;
a source electrode electrically connected to the source region, electrically insulated from the gate electrode, and arranged at least partially above the first surface;
a drain electrode electrically insulated from the second contact electrode on the second surface,
wherein the first insulation layer together with an edge of the semiconductor body forms a closed loop in a horizontal plane of the semiconductor body parallel to the first surface, and wherein the closed loop encloses the via region.

Assignees

• Hirler Franz
• Meiser Andreas Peter
• Infineon Technologies Austria

Inventors

• Hirler Franz
• Meiser Andreas Peter

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title