Electrophoretic display system

Patent metadata

Field	Value
Publication number	US-9142154-B2
Application number	US-201313854152-A
Country	US
Kind code	B2
Filing date	Apr 1, 2013
Priority date	Aug 31, 2012
Publication date	Sep 22, 2015
Grant date	Sep 22, 2015

Abstract

An electrophoretic display system includes an electrophoretic display panel, a timing controller, a data driver, and a gate driver. The data driver includes a first serial-to-parallel converter and a data converter. The first serial-to-parallel converter receives a plurality of first series data and converts the first series data into a plurality of second series data. The quantity of the second series data is more than the quantity of the first series data. The data converter receives the second series data and is electrically connected to the electrophoretic display panel. Besides, the data converter converts the second series data into display voltages, and the quantity of the display voltages is more than the quantity of the second series data. The gate driver is electrically connected to the electrophoretic display panel and the timing controller and controlled by the timing controller to provide gate driving voltages to the electrophoretic display panel.

First claim

What is claimed is:

1. An electrophoretic display system comprising:
an electrophoretic display panel;
a timing controller;
a data driver comprising:
a first serial-to-parallel converter electrically connected to the timing controller to receive a plurality of first series data and convert the first series data into a plurality of second series data, wherein the quantity of the second series data is more than the quantity of the first series data; and
a data converter electrically connected to the first serial-to-parallel converter to receive the second series data, the data converter being electrically connected to the electrophoretic display panel and converting the second series data into a plurality of display voltages, wherein the quantity of the display voltages is more than the quantity of the second series data; and

a gate driver electrically connected to the electrophoretic display panel and the timing controller and controlled by the timing controller to provide a plurality of gate driving voltages to the electrophoretic display panel,
wherein a common voltage of the electrophoretic display panel is an alternating current voltage, and
wherein the data converter comprises:
a plurality of first latch circuits electrically connected to the first serial-to-parallel converter to respectively receive a corresponding second series data of the second series data, each of the first latch circuits respectively receiving a first signal, latching one of data bits in the second series data according to a corresponding first signal of the first signals, and respectively outputting a first bit voltage;
a plurality of second latch circuits electrically connected to the first latch circuits to respectively receive the corresponding first bit voltage and receive a latch enabling signal, and each of the second latch circuits, according to the latch enabling signal, respectively latching the corresponding first bit voltage and respectively outputting a corresponding display voltage of the display voltages; and
a plurality of first shift registers for respectively providing the corresponding first signal, wherein the first shift registers are divided into a plurality of groups, and the first signals provided by the first shift registers belonging to the same group are sequentially enabled.

2. The electrophoretic display system as recited in claim 1 , wherein each of the first latch circuits comprises:
a first transistor, a first end of the first transistor receiving the corresponding second series data, a control end of the first transistor receiving the corresponding first signal;
a second transistor, a first end of the second transistor being electrically connected to a second end of the first transistor, a control end of the second transistor receiving an inverted signal of the corresponding first signal, a second end of the second transistor being electrically connected to the first end of the second transistor;
a first capacitor electrically connected between the second end of the first transistor and a ground voltage;
a third transistor, a first end of the third transistor receiving a system high voltage, a control end of the third transistor being electrically connected to the first end of the third transistor, a second end of the third transistor outputting the corresponding first bit voltage; and
a fourth transistor, a first end of the fourth transistor being electrically connected to the second end of the third transistor, a control end of the fourth transistor being electrically connected to the second end of the first transistor, a second end of the fourth transistor receiving a system low voltage.

3. The electrophoretic display system as recited in claim 2 , wherein each of the second latch circuits comprises:
a fifth transistor, a first end of the fifth transistor being electrically connected to one of the first latch circuits to receive the corresponding first bit voltage, a control end of the fifth transistor receiving the latch enabling signal;
a sixth transistor, a first end of the sixth transistor being electrically connected to a second end of the fifth transistor, a control end of the sixth transistor receiving an inverted signal of the latch enabling signal, a second end of the sixth transistor being electrically connected to the first end of the sixth transistor;
a second capacitor electrically connected between the second end of the fifth transistor and the ground voltage;
a seventh transistor, a first end of the seventh transistor receiving the system high voltage, a second end of the seventh transistor outputting the corresponding display voltage;
an eighth transistor, a first end of the eighth transistor being electrically connected to the second end of the seventh transistor, a control end of the eighth transistor being electrically connected to the second end of the fifth transistor, a second end of the eighth transistor receiving the system low voltage;
a third capacitor electrically connected between a control end of the seventh transistor and the second end of the seventh transistor; and
a ninth transistor, a first end of the ninth transistor receiving the system high voltage, a control end of the ninth transistor being electrically connected to the first end of the ninth transistor, a second end of the ninth transistor being electrically connected to the control end of the seventh transistor.

4. The electrophoretic display system as recited in claim 1 , wherein the timing controller sets the first series data within a vertical blank period, such that the data bit received by each of the first latch circuits respectively corresponds to a system low voltage.

5. An electrophoretic display system comprising:
an electrophoretic display panel;
a timing controller;
a data driver comprising:
a first serial-to-parallel converter electrically connected to the timing controller to receive a plurality of first series data and convert the first series data into a plurality of second series data, wherein the quantity of the second series data is more than the quantity of the first series data; and
a data converter electrically connected to the first serial-to-parallel converter to receive the second series data, the data converter being electrically connected to the electrophoretic display panel and converting the second series data into a plurality of display voltages, wherein the quantity of the display voltages is more than the quantity of the second series data; and

a gate driver electrically connected to the electrophoretic display panel and the timing controller and controlled by the timing controller to provide a plurality of gate driving voltages to the electrophoretic display panel,
wherein a common voltage of the electrophoretic display panel is a direct current voltage, and
wherein the data converter comprises:
a plurality of third latch circuits electrically connected to the first serial-to-parallel converter to respectively receive a corresponding second series data of the second series data, each of the third latch circuits respectively receiving a plurality of second signals, respectively latching a first data bit and a second data bit of the corresponding second series data according to the corresponding second signal, and respectively outputting a second bit voltage and a third bit voltage;
a plurality of fourth latch circuits electrically connected to the third latch circuits to respectively receive the corresponding second bit voltage and the corresponding third bit voltage and receive a latch enabling signal, and each of the fourth latch circuits, according to the latch enabling signal, respectively latching the corresponding second bit voltage and the corresponding third bit voltage and respectively outputting a first control signal and a second control si

Assignees

• Au Optronics Corp

Inventors

• Kuo Ping-Sheng
• Hwu Keh-Long
• Chan Chih-Cheng
• Lan Yung-Hsiang
• Yu Chih-Yu

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G3/344 Primary

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title