Memory element with ion conductor layer in which metal ions diffuse and memory device incorporating same

US9136470B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9136470-B2
Application numberUS-95797810-A
CountryUS
Kind codeB2
Filing dateDec 1, 2010
Priority dateDec 14, 2009
Publication dateSep 15, 2015
Grant dateSep 15, 2015

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Abstract

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The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory element comprising: a first electrode; a second electrode; and a memory layer between the first and second electrodes, wherein, (a) the memory layer comprises (1) an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and (2) two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions with respect to each other, (b) upon application of a first voltage across the first and second electrodes, metal ions diffuse into the high-resistance layers thereby effecting a detectable change in an electrical characteristic of the memory element, (c) upon application of a second voltage with a polarity different than that of the first voltage across the first and second electrodes, the metal ions dissolve in the ion source layer and the change in the electrical characteristic of the memory element is reversed, (d) the two or more high-resistance layers include (i) a first high-resistance layer which is in contact with a surface of the first electrode that faces the second electrode and extends over the entire first electrode, and (ii) a second high-resistance layer which lies between the first high-resistance layer and the ion source layer; (e) both of the first and second high resistance layers affect the change in the electrical characteristic of the memory element, and (f) only the first high-resistance layer is in contact with the first electrode. 2. The memory element according to claim 1 , wherein each of the two or more high-resistance layers is made of an oxide or nitride containing at least one element out of a group of rare-earth elements of yttrium (Y), lanthanum (La), neodymium (Nd), samarium (Sm), gadolinium (Gd), terbium (Tb), and dysprosium (Dy) or an oxide or nitride containing at least one element selected from a group of silicon (Si), aluminum (Al), titanium (Ti), and hafnium (Hf). 3. The memory element according to claim 1 , wherein the first high-resistance layer is made of gadolinium oxide (Gd—O), and the second high-resistance layer is made of a nitride or oxide of aluminum (Al) or silicon (Si). 4. The memory element according to claim 1 , wherein a resistance value is changed when a conduction path containing the metal element is formed in the memory layer by application of the first voltage to the first and second electrodes. 5. The memory element according to claim 1 , wherein the ion source layer contains aluminum (Al). 6. A memory device comprising: a plurality of memory elements each having a first electrode, a second electrode and a memory layer between the first and second electrodes; and a pulse application section that applies a pulse of voltage or current selectively to the plurality of memory elements, wherein, (a) each memory layer comprises (1) an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and (2) two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions with respect to each other, (b) upon application of a first voltage across the first and second electrodes of a memory element, metal ions diffuse into the high-resistance layers thereby effecting a detectable change in an electrical characteristic of the memory element, (c) upon application of a second voltage with a polarity different than that of the first voltage across the first and second electrodes of the memory element, the metal ions dissolve in the ion source layer and the change in the electrical characteristic of the memory element is reversed, (d) the two or more high-resistance layers include (i) a first high-resistance layer which is in contact with a surface of the first electrode that faces the second electrode and extends over the entire first electrode, and(ii) a second high-resistance layer which lies between the first high-resistance layer and the ion source layer; (e) both of the first and second high resistance layers affect the change in the electrical characteristic of the memory element, and (f) only the first high-resistance layer is in contact with the first electrode. 7. The memory device according to claim 6 , wherein at least one of the layers of the memory layer is common to all of the memory elements. 8. The memory device according to claim 7 , wherein the two or more high-resistance layers are common to all of the memory elements and each memory element has a unique first electrode, second electrode and ion source layer.

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What does patent US9136470B2 cover?
The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode…
Who is the assignee on this patent?
Maesaka Akihiro, Ohba Kazuhiro, Mizuguchi Tetsuya, and 4 more
What technology area does this patent fall under?
Primary CPC classification H01L45/085. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).