Method for the formation of a FinFET device having partially dielectric isolated Fin structure

Patent metadata

Field	Value
Publication number	US-9136384-B2
Application number	US-201314097570-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Dec 5, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

First claim

What is claimed is:

1. A FinFET device, comprising:
a substrate supporting a plurality of elongated fins formed of a first semiconductor material isolated from an underlying substrate material by an insulating layer;
a plurality of elongated gates formed of a second semiconductor material, said elongated gates extending to cross over the plurality of elongated fins at a channel region;
sidewall spacers on side walls of the elongated gates;
wherein first semiconductor materia…

Assignees

• St Microelectronics Inc

Inventors

• Loubet Nicolas
• Sampson Ronald Kevin

Classifications

• H10P50/692

  Electricity · mapped topic

• H10P30/204

  Electricity · mapped topic

• H10P30/21

  Electricity · mapped topic

• H10P14/69433

  Electricity · mapped topic

• H10P14/6334

  Electricity · mapped topic