Nonvolatile semiconductor memory device and method for manufacturing same

US9136358B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9136358-B2
Application numberUS-201314019788-A
CountryUS
Kind codeB2
Filing dateSep 6, 2013
Priority dateMar 20, 2013
Publication dateSep 15, 2015
Grant dateSep 15, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A nonvolatile semiconductor memory device comprising: a foundation layer; a stacked body provided on the foundation layer, and the stacked body including a plurality of electrode layers and a plurality of first insulating layers alternately stacked; a first semiconductor member extending in the stacked body in a stacking direction of the stacked body; a memory film provided between each of the plurality of electrode layers and the first semiconductor m…

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What does patent US9136358B2 cover?
According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second cha…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D30/0413. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).