Sputtering target, method for forming amorphous oxide thin film using the same, and method for manufacturing thin film transistor

Patent metadata

Field	Value
Publication number	US-9136338-B2
Application number	US-201313870847-A
Country	US
Kind code	B2
Filing date	Apr 25, 2013
Priority date	May 22, 2008
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

Disclosed is a sputtering target having a good appearance, which is free from white spots on the surface. The sputtering target is characterized by being composed of an oxide sintered body containing two or more kinds of homologous crystal structures.

First claim

We claim:

1. A thin film transistor, comprising
(i) a semiconductor channel layer comprising an oxide that includes Indium element (In), Gallium element (Ga), and Zinc element (Zn), and wherein said In, Ga and Zn are present in the following atom ratio;
0.1≦In/(In+Ga+Zn)≦0.9

0.05≦Ga/(In+Ga+Zn)≦0.6

0.05≦Zn/(In+Ga+Zn)≦0.9; and

(ii) an oxide resistance layer having a resistance higher than that of the semiconductor channel layer between the semiconductor channel layer and a gate insulation layer, and/or between the semiconductor channel layer and a protective layer.

2. The thin film transistor of claim 1 , wherein said In, Ga and Zn of the semiconductor channel layer are present in the following atom ratio
0.2≦In/(In+Ga+Zn)≦0.5

0.1≦Ga/(In+Ga+Zn)≦0.5

0.25≦Zn/(In+Ga+Zn)≦0.5.

3. The thin film transistor of claim 1 , wherein said In, Ga and Zn of the semiconductor channel layer are present in the following atom ratio
0.3≦In/(In+Ga+Zn)≦0.5

0.3≦Ga/(In+Ga+Zn)≦0.5

0.3≦Zn/(In+Ga+Zn)≦0.5.

4. The thin film transistor of claim 1 , wherein said In, Ga and Zn of the semiconductor channel layer are present in the following atom ratio
Ga/(In+Ga+Zn)≦0.38.

5. The thin film transistor of claim 1 , wherein said In, Ga and Zn of the semiconductor channel layer are present in the following atom ratio
Ga/(In+Ga+Zn)≦0.32.

6. The thin film transistor of claim 1 , wherein said In, Ga and Zn of the semiconductor channel layer are present in the following atom ratio
Ga/(In+Ga+Zn)≦0.23.

7. The thin film transistor of claim 1 , wherein said oxide of the semiconductor channel layer comprises a metal element (X) having positive four or more valences.

8. The thin film transistor of claim 1 , wherein said semiconductor channel layer is an amorphous film having 6.0 g/cm 3 or more of a relative density.

9. The thin film transistor of claim 1 , wherein said semiconductor channel layer is a non-degeneration semiconductor having 10 13 to 10 18 /cm 3 of a carrier concentration.

10. The thin film transistor of claim 1 , wherein a band gap of the semiconductor channel layer is 2.0 to 6.0 eV.

11. The thin film transistor of claim 1 , wherein a surface roughness of the semiconductor channel layer (RMS) is 1 nm or less.

12. The thin film transistor of claim 1 , wherein a peak showing In—X (X is In or Zn) based on radial distribution function (RDF) obtained by Grazing Incidence X-ray Scattering (GIXS) of the semiconductor channel layer is in 0.30 to 0.36 nm.

13. The thin film transistor of claim 1 , wherein an energy width (E 0 ) of a delocalized level of the semiconductor channel layer is 14 meV or less.

14. A display device comprising the thin film transistor of claim 1 .

Assignees

• Idemitsu Kosan Co

Inventors

• Yano Koki
• Kawashima Hirokazu
• Inoue Kazuyoshi

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10D30/6756

  Amorphous oxide semiconductors · CPC title