Apparatus and electronic devices including transistors comprising two-dimensional materials
US-2024339543-A1 · Oct 10, 2024 · US
Inverter logic devices including graphene field effect transistor having tunable barrier
US9136336B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136336-B2 |
| Application number | US-201213593708-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 24, 2012 |
| Priority date | Aug 26, 2011 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.
First claim
Opening claim text (preview).
What is claimed is: 1. An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physically separated from each other by a gap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each o…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D62/882Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136336B2 cover?
- Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an outp…
- Who is the assignee on this patent?
- Heo Jin-Seong, Park Seong-Jun, Chung Hyun-Jong, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D62/882. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).