Manufacturing method for semiconductor structure
US-12165910-B2 · Dec 10, 2024 · US
Semiconductor constructions
US9136331B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136331-B2 |
| Application number | US-201313860427-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 10, 2013 |
| Priority date | Apr 10, 2013 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.
First claim
Opening claim text (preview).
We claim: 1. A semiconductor construction comprising a semiconductor material patterned into two mesas spaced from one another by at least one dummy projection comprising the semiconductor material; the dummy projection having a width along a cross-section of X and each of the mesas having a width along the cross-section of at least about 3X; at least some of the semiconductor material within the mesas being conductively-doped. 2. The semiconductor construction…
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Electricity · mapped topic
Electricity · mapped topic
- H10W10/014Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136331B2 cover?
- Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).