Structure and method to form liner silicide with improved contact resistance and reliablity
US-2015380305-A1 · Dec 31, 2015 · US
Three dimensional stacked semiconductor structure and method for manufacturing the same
US9136277B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136277-B2 |
| Application number | US-201213652701-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 16, 2012 |
| Priority date | Oct 16, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
Official abstract text for this publication.
A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.
First claim
Opening claim text (preview).
What is claimed is: 1. A 3D stacked semiconductor structure, comprising: a plurality of oxide layers and a plurality of conductive layers arranged alternately; at least a contact hole formed vertically to the oxide layers and the conductive layers, and the contact hole extending to and stopping at one of the conductive layers; a cavity, communicating with the contact hole, formed at the corresponding conductive layer by removing at least one portion of the corresponding conduc…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/066Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136277B2 cover?
- A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the co…
- Who is the assignee on this patent?
- Macronix Int Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/066. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).