Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking

Patent metadata

Field	Value
Publication number	US-9136259-B2
Application number	US-10177608-A
Country	US
Kind code	B2
Filing date	Apr 11, 2008
Priority date	Apr 11, 2008
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.

First claim

What is claimed is:

1. A method of forming a die stack, comprising:
forming a plurality of through-wafer vias extending through a planar surface of a first die;
forming one or more alignment features directly on a first surface of the first die, wherein the first surface comprises the planar surface of the first die, wherein the one or more alignment features are electrically separate from and non-conducting with the through-wafer vias, wherein none of the plurality of through-w…

Assignees

• Pratt Dave
• Micron Technology Inc

Inventors

• Pratt Dave

Classifications

• H10W90/722

  Electricity · mapped topic

• H10W90/297

  Electricity · mapped topic

• H10W80/168

  Electricity · mapped topic

• H10W72/07236

  Electricity · mapped topic

• H10W72/07227

  Electricity · mapped topic