Semiconductor device
US-2024421048-A1 · Dec 19, 2024 · US
Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
US9136256B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136256-B2 |
| Application number | US-201414185502-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 20, 2014 |
| Priority date | Feb 20, 2014 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Power supply system ( 100 ) comprises vertically sequentially a QFN leadframe ( 101 ), a first chip ( 110 ) with FET terminals on opposite sides, a flat interposer ( 120 ), and a second chip ( 130 ) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad ( 107 ) has a portion ( 107 a ) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.
First claim
Opening claim text (preview).
I claim: 1. A method for fabricating a power supply system comprising the steps of: providing a leadframe having leads and a pad with a first and a second surface, the second surface having a portion recessed for a pocket with a depth and an outline suitable for attaching a semiconductor chip; providing a first chip with FET source and gate terminals on one side and FET drain terminal on the opposite side; attaching the source terminal of the first FET chip onto the recessed s…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9136256B2 cover?
- Power supply system ( 100 ) comprises vertically sequentially a QFN leadframe ( 101 ), a first chip ( 110 ) with FET terminals on opposite sides, a flat interposer ( 120 ), and a second chip ( 130 ) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad ( 107 ) has a portion ( 107 a ) recessed as pocket with a depth and an outline sui…
- Who is the assignee on this patent?
- Texas Instruments Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W90/811. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).