Methods of fabricating package stack structure and method of mounting package stack structure on system board

Patent metadata

Field	Value
Publication number	US-9136255-B2
Application number	US-201414196577-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Sep 27, 2010
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

First claim

What is claimed is:

1. A package stack structure comprising:
a first package including a first, semiconductor chip, a first package substrate, and a first molding compound, the first semiconductor chip disposed on the first package substrate, wherein sides of the first semiconductor chip are surrounded by the first molding compound, and a top surface of the first semiconductor chip is exposed;
a second package including a second semiconductor chip, a second package substrate, an…

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sun-Kyoung
• Choi Eun-Jin

Classifications

• H10W90/754

  Electricity · mapped topic

• H10W90/752

  Electricity · mapped topic

• H10W90/734

  Electricity · mapped topic

• H10W90/732

  Electricity · mapped topic

• H10W90/724

  Electricity · mapped topic