Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Multi-chip stacked package and method for forming the same
US9136248B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136248-B2 |
| Application number | US-201414521809-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 23, 2014 |
| Priority date | Oct 25, 2013 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
Official abstract text for this publication.
The present disclosure relates to a multi-chip stacked package and a method for forming the same. The package comprises a chip carrier and multiple levels of chips, with one or more chips being arranged in each level, wherein one or more levels of chips, except for the topmost chips, have conductive vias, a patterned conductor layer is arranged on a back surface of a lower one of two chips in two adjacent levels, conductive bumps are provided between two adjacent levels of chips, and the conductive vias of a lower chip are electrically coupled to an upper chip by means of the patterned conductor layer and the conductive bumps. In the present disclosure, electrical connections are redistributed by means of the patterned conductor layer, and are further used for coupling multiple levels of chips by means of the conductive bumps. The resultant chip has a reduced chip size and can be used for electrically coupling various levels of chips, which achieves flexible electrical connections.
First claim
Opening claim text (preview).
What is claimed is: 1. A multi-chip stacked package comprising: a chip carrier; multiple levels of chips, with one or more chips being arranged in each level and; a patterned conductor layer on a back surface of a lower one of two chips in two adjacent levels; a plurality of first conductive bumps between at least one lowermost chip and said chip carrier, a plurality of second conductive bumps between two adjacent levels of chips; and wherein one or more levels of chips,…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136248B2 cover?
- The present disclosure relates to a multi-chip stacked package and a method for forming the same. The package comprises a chip carrier and multiple levels of chips, with one or more chips being arranged in each level, wherein one or more levels of chips, except for the topmost chips, have conductive vias, a patterned conductor layer is arranged on a back surface of a lower one of two chips in t…
- Who is the assignee on this patent?
- Silergy Semiconductor Technology Hangzhou Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).