Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9136181-B2
Application number	US-201214355919-A
Country	US
Kind code	B2
Filing date	Dec 7, 2012
Priority date	Nov 30, 2012
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
defining active regions on a semiconductor substrate;
forming an interfacial oxide layer on a surface of the semiconductor substrate;
forming a high-K gate dielectric on the interfacial oxide layer;
forming a first metal gate layer on the high-K gate dielectric;
forming a dummy gate layer on the first metal gate layer;
patterning the dummy gate layer and/or the first metal gate layer and/or the h…

Assignees

• Inst Of Microelectronics Cas

Inventors

• Xu Qiuxia
• Zhu Huilong
• Xu Gaobo
• Zhou Huajie
• Chen Dapeng

Classifications

• H10P95/90

  Electricity · mapped topic

• H10P95/06

  Electricity · mapped topic

• H10P52/403

  Electricity · mapped topic

• H10P50/00

  Electricity · mapped topic

• H10P30/22

  Electricity · mapped topic