Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology

Patent metadata

Field	Value
Publication number	US-9136129-B2
Application number	US-201314041591-A
Country	US
Kind code	B2
Filing date	Sep 30, 2013
Priority date	Sep 30, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

First claim

What is claimed is:

1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region, comprising:
forming an NVM structure in the NVM region, wherein the NVM structure comprises a control gate structure and a select gate structure;
forming a protective layer over the NVM structure;
forming a gate dielectric layer over the substrate in the log…

Assignees

• Freescale Semiconductor Inc

Inventors

• Perera Asanga H

Classifications

• H10D64/037

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic

• H10D30/0411

  Electricity · mapped topic

• H10D64/035 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic