Processing method and apparatus for check pin of memory, device, storage medium, and computer program product
US-2024274163-A1 · Aug 15, 2024 · US
Semiconductor memory apparatus
US9136016B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136016-B2 |
| Application number | US-201414210654-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 14, 2014 |
| Priority date | Nov 29, 2013 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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A semiconductor memory apparatus includes a latch section including a plurality of latches configured to store test data, a control signal generation part configured to generate a mode selection signal in response to a latch address signal and a first mode signal, and an output circuit configured to operate in accordance with a training enable signal, and generate at least a subset of test data output by each of the plurality of latches in response to a latch selection signal, the mode selection signal, and a second mode signal.
First claim
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What is claimed is: 1. A semiconductor memory apparatus comprising: a latch section including a plurality of latches configured to store test data; a control signal generation part configured to generate a data output mode selection signal in response to a latch address signal and a first data output mode signal; and an output circuit configured to operate in accordance with a training enable signal and generate at least a subset of test data output by each of the plurality of…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9136016B2 cover?
- A semiconductor memory apparatus includes a latch section including a plurality of latches configured to store test data, a control signal generation part configured to generate a mode selection signal in response to a latch address signal and a first mode signal, and an output circuit configured to operate in accordance with a training enable signal, and generate at least a subset of test data…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C29/022. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).