Closed-loop high-speed channel equalizer adaptation

Patent metadata

Field	Value
Publication number	US-9130792-B2
Application number	US-201414299187-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jun 10, 2013
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

A serial communication circuit (FIG. 3 ) is disclosed. The circuit includes an equalizer circuit ( 306 ) arranged to receive a data signal (CH 1 ) and produce an equalized data signal. A log detector circuit ( 300 ) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit ( 332 ) receives the power signal and produces a select signal. A first selection circuit ( 336 ) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

First claim

What is claimed is:

1. A method of equalizing a data signal, comprising:
receiving a plurality of data signals;
producing a plurality of power signals indicating a power level of each respective data signal;
producing a select signal in response to the plurality of power signals;
selecting a first correction signal from a first plurality of correction signals in response to the select signal;
selecting a second correction signal from a second plurality of correction signal…

Assignees

• Texas Instruments Inc

Inventors

• Sperlich Roland
• Huang Huanzhang
• Branch Charles M

Classifications

• H04L25/026 Primary

  Electricity · mapped topic

• H04B3/144

  Electricity · mapped topic

• H04L25/03019 Primary

  Electricity · mapped topic

• H04L25/03885

  Electricity · mapped topic

• H04L27/01 Primary

  Electricity · mapped topic