Redundant delay digital-to-time converter

Patent metadata

Field	Value
Publication number	US-9130588-B2
Application number	US-201313839480-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

First claim

What is claimed is:

1. An apparatus configured to receive an input signal and a digital value representative of a target time delay and to provide a representation of the input signal delayed by the target time delay, the apparatus comprising:
a control module configured to receive the digital value;
a coarse delay stage arranged to receive the input signal and to provide a coarse delayed representation of the input signal using a selected coarse delay interval, the selected co…

Assignees

• Intel Mobile Comm Gmbh

Inventors

• Henzler Stephan
• Schimper Markus
• Madoglio Paolo
• Pellerano Stefano
• Chandrashekar Kailash

Classifications

• H03M1/82 Primary

  Electricity · mapped topic

• H03K5/131

  Electricity · mapped topic

• H03L7/08

  Electricity · mapped topic