Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
US-9503066-B2 · Nov 22, 2016 · US
US9130552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9130552-B2 |
| Application number | US-201314072142-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2013 |
| Priority date | Nov 5, 2013 |
| Publication date | Sep 8, 2015 |
| Grant date | Sep 8, 2015 |
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An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch respectively of an integrated circuit switching regulator. The detector monitors both the rising edge and the trailing edge of each of the high-drive and the low-drive signals respectively to determine a timing overlap between the signals and generates a detection signal indicating a dead-time value proportional to the presence or absence of the timing overlap between the signals. An output circuit can be configured to process the detection signal from the detector to enable a correction of the timing overlap between the signals if timing overlap is detected.
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What is claimed is: 1. An integrated circuit comprising: a detector configured to monitor a high-drive signal and a low-drive signal that drive a high-side switch and a low-side switch, respectively, of a switching regulator that is part of the integrated circuit, wherein the detector monitors both a rising edge and a trailing edge of each of the high-drive and the low-drive signals, respectively, to determine a timing overlap between the signals, and to generate a detection signa…
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