Decoder for decoding PWM code and communications system

Patent metadata

Field	Value
Publication number	US-9130551-B2
Application number	US-201313954069-A
Country	US
Kind code	B2
Filing date	Jul 30, 2013
Priority date	Jul 31, 2012
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.

First claim

What is claimed is:

1. A decoder for decoding an input signal coded with a pulse width modulation (PWM) code as a line code to an output signal in a binary code, the input signal in a transmission line being outputted from a clock master or a normal node communicating with each other via the transmission line, the decoder comprising:
a first memory on which information on a duty duration of the PWM code is stored, a first signal and a second signal in the PWM code being assigned with the respective signals in the binary code depending on their duty ratio, the duty ratio being the ratio of the duty duration to a pulse period, the first signal being supplied from the clock master, the second signal being generated by changing the supplied first signal by the normal node, the information on the duty duration of the first signal being stored on the first memory;
a first timer that measures the duty duration of the input signal;
a determination circuit that determines which output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer;
a first controller that updates the information stored on the first memory, on the basis of the determination result and the measured duty duration.

2. The decoder according to claim 1 , wherein,
the determination circuit comprises:
a setting circuit that sets a decoding threshold value for decoding the input signal, on the basis of the information stored on the first memory; and
a comparator that compares the duty duration counted with the first timer with the decoding threshold value to determine the output signal.

3. The decoder according to claim 1 , wherein,
the first controller is configured to update the information on the first memory, every time the determination circuit determines the input signal corresponds to the stored output signal.

4. The decoder according to claim 1 , wherein,
the PWM code has two signals different in duty ratio, and each signal in the PWM code corresponds to a respective signal in the binary code.

5. A decoder for decoding an input signal coded with a pulse width modulation (PWM) code as a line code to an output signal in a binary code, comprising:
a first memory on which information on a duty duration of the PWM code is stored, signals in the PWM code being assigned with the respective signals in the binary code depending on their duty ratio, the duty ratio being the ratio of the duty duration to a pulse period;
a first timer that measures the duty duration of the input signal;
a determination circuit that determines which output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer; and
a first controller that updates the information stored on the first memory, on the basis of the determination result and the measured duty duration, the first controller being configured to delete the information stored on the first memory and to store a new duty duration measured by the first timer on the first memory, when a number of bits which the determination circuit have determined as a same input signals continuously exceeds a predetermined upper limit.

6. A decoder for decoding an input signal coded with a pulse width modulation (PWM) code as a line code to an output signal in a binary code, comprising:
a first memory on which information on a duty duration of the PWM code is stored, signals in the PWM code being assigned with the respective signals in the binary code depending on their duty ratio, the duty ratio being the ratio of the duty duration to a pulse period;
a first timer that measures the duty duration of the input signal;
a determination circuit that determines which output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer;
a first controller that updates the information stored on the first memory, on the basis of the determination result and the measured duty duration; and
a second timer that measures the pulse period of the input signal,
wherein, the determination circuit comprises:
a setting circuit that sets a decoding threshold value for decoding the input signal, on the basis of the information stored on the first memory and the pulse period measured with the second timer; and
a comparator that compares the duty duration counted with the first timer with the decoding threshold value to determine the output signal.

7. A communications system, comprising:
nodes that communicate with each other via a transmission line on which a pulse width modulation (PWM) code is used, nodes including a clock master and normal nodes, the clock master supplying a first signal in the PWM code to the transmission line, the normal nodes, changing the first signal to a second signal in the PWM code; and
a decoder provided in at least one normal node, the decoder decoding an input signal from the transmission line to an output signal in a binary code, the first and the second signals in the PWM code being assigned with the respective signals in the binary code depending on their duty ratio, the duty ratio being the ratio of a duty duration to a pulse period;
wherein the decoder comprising:
a first memory on which information on the duty duration of the first signal of the PWM code is stored;
a first timer that measures the duty duration of the input signal received in the own node;
a determination circuit that determines which output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer;
a first controller that updates the information stored on the first memory, on the basis of the determination result and the measured duty duration.

Assignees

• Denso Corp

Inventors

• Kashima Hideki
• Kishigami Tomohisa
• Kaneko Naoji

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title