Processor that transitions to an idle mode when no task is scheduled to execute and further enters a quiescent doze mode or a wait mode depending on the value of a reference counter

Patent metadata

Field	Value
Publication number	US-9128703-B1
Application number	US-26198008-A
Country	US
Kind code	B1
Filing date	Oct 30, 2008
Priority date	Oct 30, 2008
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

A quiescent doze mode permits significant reductions in power consumption and dissipation by electronic devices while idle without producing adverse latencies to users. Device drivers communicate predictions as to future use of their coupled devices with a kernel. The kernel may then enter a quiescent doze mode comprising gating clocks on the processor and peripherals, disabling interrupts, and executing a wait for interrupt. Dynamically increasing timer interrupt intervals to significant fractions or multiples of a second further increases the percentage of time the device remains in quiescent doze mode.

First claim

What is claimed is:

1. A method for placing an e-book reader into a low power mode, the method comprising:
transitioning a processor from an active mode to an idle mode when no task is scheduled to execute on the processor;
setting a timer interrupt interval based on when a next task is to be executed;
adjusting a reference counter in a kernel executing on the processor, the adjusting comprising:
incrementing the reference counter based on a device driver indicating that a device will be used within a predetermined time period, and
decrementing the reference counter in the kernel based on the device driver indicating that the device will not be used within the predetermined time period;

entering a wait mode during the timer interrupt interval when the reference counter is greater than zero, the wait mode comprising stopping a clock for the processor while leaving the device active;
entering a quiescent doze mode during the timer interrupt interval when the reference counter is zero, the quiescent doze mode including:
gating an external memory interface clock associated with an external memory interface that provides access to an external memory; and
placing the external memory into self refresh; and
waiting for an interrupt before resuming the active mode.

2. The method of claim 1 , wherein the quiescent doze mode further comprises maintaining logic circuits in a powered state.

3. The method of claim 1 , wherein the kernel comprises a Linux-based kernel.

4. The method of claim 1 , wherein the quiescent doze mode further comprises gating at least one of the following:
a universal serial bus clock;
an image processing unit clock;
one or more clocks in a clock gating register;
a random number generator clock;
a watchdog clock;
a real-time clock; and
a device identification clock.

5. A method comprising:
testing, during a timer interrupt interval, a reference counter corresponding to a device associated with a device driver in a kernel, the reference counter updated by the device driver based on at least one pending use of the device as determined by the device driver;
predicting an anticipated usage of the device based at least on the reference counter updated by the device driver; and
instructing, during the timer interrupt interval, a processor to enter a quiescent doze mode when no anticipated usage of the device is predicted, the quiescent doze mode including:
placing an external memory into self refresh; and
after placing the external memory into self refresh, gating or shutting down one or more devices external to the processor.

6. The method of claim 5 , further comprising executing a wait for interrupt after placing the external memory into self refresh.

7. The method of claim 5 , further comprising setting a processor timer interrupt interval to occur on demand.

8. The method of claim 5 , further comprising setting a processor timer interrupt interval dynamically to when the next task is to be executed.

9. The method of claim 8 , wherein the processor timer interrupt interval is at least 5 ms and at most 1000 ms.

10. The method of claim 8 , wherein the processor timer interrupt interval is at least 5 ms and at most 250 mc.

11. The method of claim 5 , wherein the predicted anticipated usage information further comprises testing at least a second reference counter for a second device.

12. The method of claim 5 , wherein the quiescent doze mode further comprises:
gating at least one of the following:
a smart directory memory access dock;
a universal serial bus clock;
an image processing unit clock; and
an external memory interface clock;
disabling processor generated interrupts; and
waiting for an interrupt before resuming an active mode.

13. The method of claim 5 , wherein the quiescent doze mode further comprises gating a smart direct memory access clock and placing the external memory into self refresh.

14. A system for reducing power consumption in a portable electronic device, the system comprising:
memory;
a processor couple to the memory;
a peripheral device coupled to the processor:
a device driver stored in memory coupled with the peripheral device, the device driver being configured to execute on the processor and to increment a reference counter when the peripheral device is scheduled to be utilized or decrement the reference counter when the peripheral device is not scheduled to be utilized; and
a kernel stored in the memory and configured to execute on the processor, the kernel being configured to communicate with the device driver, and when the processor is idle and the device driver reference counter is greater than zero, to place the processor into a wait mode, the wait mode comprising stopping a clock for the processor while leaving the peripheral device active, and when the processor is idle and the device driver reference counter is zero, to place the processor and the peripheral device into a quiescent doze mode, the quiescent doze mode including:
placing an external memory into self refresh; and
after placing the external memory into self refresh, gating or shutting down one or more devices external to the processor.

15. The system of claim 14 , further comprising a timer interrupt in the processor configured to send one or more interrupts on demand.

16. The system of claim 14 , further comprising a timer interrupt interval in the processor configured to be dynamically adjusted based on when a next task is to be executed.

17. The system of claim 14 , wherein the quiescent doze mode further comprises:
gating at least one of the following:
a smart direct memory access clock;
a universal serial bus clock;
an image processing unit clock; and
an external memory interface clock;
disabling processor generated interrupts; and
waiting for an interrupt before resuming an active mode.

18. One or more non-transitory computer-readable storage media comprising:
a device driver configured to update a reference counter for a device based on a determination of when the device is not expected to be utilized; and
a kernel configured to:
interrogate the reference counter
set a timer interrupt interval on a processor to when the next task is to be executed; and
enter a quiescent doze mode during the timer interrupt interval when, based on the interrogation, the device is not expected to be utilized, the quiescent doze mode including:
gating an external memory interface clock associated with an external memory interface that provides access to an external memory; and
placing the external memory into self refresh.

19. The one or more non-transitory computer-readable storage media of claim 18 , wherein the kernel is further configured, in the quiescent doze mode, to gate all unused system clocks, disable interrupts and enter a wait for interrupt state.

20. The method of claim 1 , further comprising entering a wait mode when the reference counter is greater than zero, the wait mode including stopping a clock associated with the processor while leaving one or more devices active; and
waiting for an interrupt before resuming the active mode.

Assignees

• Lachwani Manish
• Berbessou David
• Amazon Tech Inc

Inventors

• Lachwani Manish
• Berbessou David

Classifications

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title