Package-aware state-based leakage power reduction
US-2016329895-A1 · Nov 10, 2016 · US
Reconfigurable flip-flop
US9124262B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9124262-B2 |
| Application number | US-201313927936-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 26, 2013 |
| Priority date | Sep 6, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
Official abstract text for this publication.
A device ( 300, 1000 ) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements ( 340, 360, 1040, 1060 ) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements ( 340, 360, 1040, 1060 ) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).
First claim
Opening claim text (preview).
What is claimed is: 1. A reconfigurable flip-flop circuit, comprising: an input; a common output; a first storage element including an input electrically coupled to the input through at least a first storage element input switch, and an output electrically coupled to a first storage element output switch; a second storage element including an input electrically coupled to the input through at least a second storage element input switch, and an output electrically coupled to…
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- H03K3/356156Primary
Electricity · mapped topic
- H03K3/3568Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9124262B2 cover?
- A device ( 300, 1000 ) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements ( 340, 360, 1040, 1060 ) are operating in series to provide a MUX-D flip-flop. In a second configuration, th…
- Who is the assignee on this patent?
- Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K3/356156. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).