Defect capping method for reduced defect density epitaxial articles
US-9218954-B2 · Dec 22, 2015 · US
Method of manufacturing semiconductor wafers
US9123795B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123795-B2 |
| Application number | US-201314087883-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 22, 2013 |
| Priority date | Dec 4, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.
First claim
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What is claimed is: 1. A method of manufacturing semiconductor wafers, in which a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method comprising the following steps: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a…
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- What does patent US9123795B2 cover?
- A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat line…
- Who is the assignee on this patent?
- Fujikoshi Machinery Corp, Nat Inst Of Advanced Ind Scien
- What technology area does this patent fall under?
- Primary CPC classification H10P90/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).