Through-silicon via unit cell with keep out zones and center point aligned probe pad, and method of forming

Patent metadata

Field	Value
Publication number	US-9123787-B2
Application number	US-201314028729-A
Country	US
Kind code	B2
Filing date	Sep 17, 2013
Priority date	Sep 17, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate;
a through-silicon via (TSV) disposed within the semiconductor substrate;
a plurality of V0 vias disposed on the TSV, wherein the plurality of V0 vias comprise a V0 unit cell, and wherein the V0 unit cell comprises at least two keep out zones; and
a probe pad disposed on the V0 unit cell, wherein the probe pad comprises a first set of metal lines and a second set of metal lines, wherein th…

Assignees

• Globalfoundries Inc

Inventors

• Kamineni Himani S
• Alapati Ramakanth
• Balicka Maria

Classifications

• H10W70/635

  Electricity · mapped topic

• H10W20/20

  Electricity · mapped topic

• H10W20/069 Primary

  Electricity · mapped topic

• G06F30/394 Primary

  Physics · mapped topic

• H01L23/49827

  Electricity · mapped topic